AD872A Analog Devices, AD872A Datasheet
AD872A
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AD872A Summary of contents
Page 1
... The AD872A is fabricated on Analog Devices’ ABCMOS-l process that utilizes high speed bipolar and CMOS transistors on a single chip. The AD872A is packaged in a 28-lead ceramic DIP and a 44- terminal leadless ceramic surface mount package (LCC). Opera- tion is specified from +70 C and – +125 C. ...
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... AD872A–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION MAX CONVERSION RATE INPUT REFERRED NOISE ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) No Missing Codes 2 Zero Error (@ + Gain Error (@ +25 C) TEMPERATURE DRIFT Zero Error 3, 4 Gain Error 3, 5 Gain Error 6 POWER SUPPLY REJECTION ...
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... MHz unless otherwise noted) SS SAMPLE J, S Grades +2.0 +0.8 115 115 5 +2.4 +0 AD872A 1 Units dB typ dB min dB typ dB typ dB typ dB typ dB max dB typ dB typ dB typ dB typ dB typ MHz typ MHz typ ns typ ps rms typ ns typ ns typ Units ...
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... AD872A SWITCHING SPECIFICATIONS Parameter 1 Clock Period CLOCK Pulsewidth High CLOCK Pulsewidth Low 2 Clock Duty Cycle Output Delay Pipeline Delay (Latency) Data Access Time (LCC Package Only) Output Float Delay (LCC Package Only) NOTES 1 Conversion rate is operational down to 10 kHz without degradation in specified performance. ...
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... Out of Range is Active HIGH on the leading edge of Code 0 or the trailing edge of Code 4096. See Output Data Format Table III. DI Clock Input. The AD872A will initiate a conversion on the rising edge of the clock input. See the Timing Diagram for details. AO +2.5 V Reference Output. Tie to REF IN for normal operation. ...
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... ORDERING GUIDE Model Temperature Range AD872AJD +70 C AD872AJE + AD872ASD – +125 C 2 AD872ASE – +125 C NOTES Ceramic DIP Leadless Ceramic Chip Carrier. 2 MIL-STD-883 version will be available; contact factory. –6– 1 Package Option D-28 E-44A ...
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... Figure 2. AD872A S/(N+D) Input Frequency 1 Figure 4. AD872A Typical FFT Figure 5. AD872A Typical FFT, f REV. A –70 –0.5 dB –75 –80 –6.0 dB –85 –90 – Figure 3. AD872A Distortion vs. Input Frequency, Full-Scale Input f = 1MHz IN f AMPLITUDE = –0.5dB IN THD = 73dB S/(N+D) = 68dB SNR = 70dB SFDR = 73dB ...
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... DEVIATION FROM CORRECT CODE – LSB Figure 8. AD872A Output Code Histogram for DC Input f = 750kHz IN f AMPLITUDE = –0.5dB IN THD = –74dB S/(N+D) = 69dB SNR = 71dB SFDR = 75dB Figure 6. AD872A Typical FFT, f ...
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... The AD872A clock circuitry uses both edges of the clock in its internal timing circuitry (see spec page for exact timing require- ments). The AD872A samples the analog input on the rising edge of the clock input ...
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... Figure 15. Single-Ended to Differential Connections; U1 AD811 or AD9617 The use of the differential input signal can help to minimize even-order distortion from the input THA where performance beyond – desired. Figure 16 shows the AD872A large signal (–0.5 dB) and small signal (–20 dB) frequency response – ...
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... Because of the THA’s exceptionally wide input bandwidth, some users may find the AD872A is sensitive to noise at fre- quencies from 10 MHz to 50 MHz that other converters are incapable of responding to. This sensitivity can be mitigated by careful use of the differential inputs (see previous paragraphs) ...
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... MSB pin. In the 44-terminal surface mount packages, both MSB and MSB bits are provided. The AD872A features a digital out-of-range (OTR) bit that goes high when the input exceeds positive full scale or falls below negative full scale. As Table III indicates, the output bits will be set appropriately according to whether out-of-range high – ...
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... The digital outputs can be placed into a three-state mode by pulling the OUTPUT ENABLE (OEN) pin LOW. Note that this function is not intended to be used to pull the AD872A on and off a bus at 10 MHz. Rather intended to allow the ADC to be pulled off the bus for evaluation or test modes. Also, to ...
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... The AD872A is factory trimmed to minimize zero error, gain error and linearity errors. In some applications the zero and gain DV errors of the AD872A need to be externally adjusted to zero required, both zero error and gain error can be trimmed with ex- ternal potentiometers as shown in Figure 31. Note that gain er- ror adjustments must be made with an external reference ...
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... AD568 12-bit, high speed digital-to-analog converter (DAC). This circuit can be used for applications requiring offset adjust- ments on every clock cycle. The AD568 connection scheme is used to provide a –0.512 V to +0.512 V output range. The off- set voltage must be stable on the rising edge of the AD872A clock input ...
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... NOTE: JP11 SHOULD BE OPEN C22 0.1 TP5 +5VA FB1 0.1 0.01 AGND 0.1 0.01 –5VA FB2 TP6 FB3 +5VD C3 C10 C6 0. 0.1 DGND Figure 34. AD872A/AD871 Evaluation Board Schematic +5D CLOCK INPUT C13 C14 0.1 0.1 6 DGND U3 +5D 74HC04 5 22 AGND DRV DD C16 C15 0.1 0.1 23 DGND ...
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... Resistor, 1%, Metal Film, 20 SMD Chip Capacitor, 0.01 F Capacitor, Tantalum Capacitor, Tantalum SMD Chip Capacitor, 0.1 F Capacitor, Mica Capacitor, Ceramic AD872A REF43B 74HC04N Ferrite Bead BNC Jack Jumpers Headers 40-Pin IDC Connector –17– AD872A Quantity ...
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... AD872A Figure 36. Component Side PCB Layout (Not Shown to Scale) Figure 37. Solder Side PCB Layout (Not Shown to Scale) –18– REV. A ...
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... Figure 38. Ground Layer PCB Layout (Not Shown to Scale) Figure 39. Power Layer PCB Layout (Not Shown to Scale) REV. A –19– AD872A ...
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... AD872A PIN 1 0.225 (5.72) MAX 0.200 (5.08) 0.125 (3.18) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Side Brazed DIP (D-28) 0.005 (0.13) MIN 0.100 (2.54) MAX 28 15 0.610 (15.49) 0.500 (12.70 0.060 (1.52) 1.490 (37.85) MAX 0.015 (0.38) 0.026 (0.66) 0.110 (2.79) 0.070 (1.78) SEATING PLANE 0.014 (0.36) 0.090 (2.29) 0.030 (0.76) 44-Terminal LCC (E-44A) 0.100 (2.54) 0.055 (1.40) ...