AD9281ARS Analog Devices Inc, AD9281ARS Datasheet
AD9281ARS
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AD9281ARS Summary of contents
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FEATURES Complete Dual Matching ADC Low Power Dissipation: 225 mW (+3 V Supply) Single Supply: 2 5.5 V Differential Nonlinearity Error: 0.1 LSB On-Chip Analog Input Buffers On-Chip Reference Signal-to-Noise Ratio: 49.2 dB Over Seven Effective Bits ...
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AD9281–SPECIFICATIONS Parameter RESOLUTION CONVERSION RATE DC ACCURACY Differential Nonlinearity Integral Nonlinearity 1 Differential Nonlinearity (SE) 1 Integral Nonlinearity (SE) Zero-Scale Error, Offset Error Full-Scale Error, Gain Error Gain Match Offset Match ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay ...
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Parameter 1 DYNAMIC PERFORMANCE (SE) Signal-to-Noise and Distortion f = 3.58 MHz Signal-to-Noise f = 3.58 MHz Total Harmonic Distortion f = 3.58 MHz Spurious Free Dynamic Range f = 3.58 MHz DIGITAL INPUTS High Input Voltage Low Input Voltage ...
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AD9281 ABSOLUTE MAXIMUM RATINGS* With Respect Parameter to Min AVDD AVSS –0.3 DVDD DVSS –0.3 AVSS DVSS –0.3 AVDD DVDD –6.5 CLK AVSS –0.3 Digital Outputs DVSS –0.3 AINA, AINB AVSS –1.0 VREF AVSS –0.3 REFSENSE AVSS –0.3 REFT, REFB ...
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AVDD DRVDD DRVSS AVSS a. D0–D9 AVDD AVDD IN AVSS AVSS d. INA, INB OFFSET ERROR The first transition should occur at a level 1 LSB above “zero.” Offset is defined as the deviation of the actual first code transi- ...
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AD9281 –Typical Characteristic Curves (AVDD = +3 V, DVDD = + MHz (50% duty cycle input span from –0 +1 internal reference unless otherwise noted –1 ...
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CLOCK FREQUENCY – Hz Figure 9. THD vs. Clock Frequency 1.013 1.012 1.011 1.010 1.009 1.008 –40 – TEMPERATURE – C Figure 10. Voltage ...
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AD9281 10.0 FUND 0.0 –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 3RD –70.0 2ND 9TH 8TH –80.0 –90.0 –100.0 –110.0 0.0E+0 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.0E+6 14.0E+6 Figure 15a. Simultaneous Operation of I and Q Channels 10.0 FUND 0.0 –10.0 ...
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The AD9281 can accommodate a variety of input spans be- tween 1 V and 2 V. For spans of less than 1 V, expect a propor- tionate degradation in SNR. Use span will provide the best ...
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AD9281 REFERENCE AND REFERENCE BUFFER The reference and buffer circuitry on the AD9281 is configured for maximum convenience and flexibility. An illustration of the equivalent reference circuit is show in Figure 26. The user can select from five different reference ...
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ADC CORE 0.1 F IREFT IREFB 0.1 F VREF 1.0 F 0.1 F 10k REFSENSE INTERNAL CONTROL 10k LOGIC AVSS AD9281 Figure 26. Reference Buffer Equivalent Circuit and External Decoupling Recommendation For best results in ...
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AD9281 DIGITAL INPUTS AND OUTPUTS Each of the AD9281 digital control inputs, CHIP SELECT, CLOCK, SELECT and SLEEP are referenced to AVDD and AVSS. Switching thresholds will be AVDD/2. The format of the digital output is straight binary. A low ...
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At the receiver, the demodulation of a QAM signal back into its separate I and Q components is essentially the modulation process explain above but in the reverse order. A common and traditional implementation of a QAM demodulator is shown ...
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AD9281 REVISION HISTORY 1/11—Rev Rev. F Updated Format .................................................................. Universal Changes to Pin Configuration Diagram ........................................ 4 Changes to Pin Function Descriptions Table ................................ 4 Removed Evaluation Boards; Renumbered Sequentially ............................................................................ Changes to Ordering Guide ...
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... Temperature Range AD9281ARS −40°C to +85°C AD9281ARSRL −40°C to +85°C AD9281ARSZ −40°C to +85°C AD9281ARSZRL −40°C to +85° RoHS Compliant Part Shrink Small Outline. ©1999–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...