AD9754ARU Analog Devices Inc, AD9754ARU Datasheet
AD9754ARU
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AD9754ARU Summary of contents
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FEATURES High Performance Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 14-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 5 MHz Output: 83 dBc Differential Current Outputs Power ...
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AD9754–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL + Differential Nonlinearity (DNL + ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error ...
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DYNAMIC SPECIFICATIONS Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f CLOCK Output Settling Time (t ) (to 0.1%) ST Output Propagation Delay ( Glitch Impulse 1 Output Rise Time (10% to 90%) 1 Output Fall Time (10% to ...
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... LPW IOUTA OR IOUTB 0.1% Figure 1. Timing Diagram Max Units Model +6.5 V AD9754AR +6.5 V AD9754ARU – +85 C +0.3 V AD9754-EB +6 Small Outline IC Thin Shrink Small Outline Package. DVDD + 0.3 V DVDD + 0.3 V THERMAL CHARACTERISTICS AVDD + 0.3 V Thermal Resistance AVDD + 0.3 V 28-Lead 300 Mil SOIC AVDD + 0 ...
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Pin No. Name Description 1 DB13 Most Significant Data Bit (MSB). 2–13 DB12–DB1 Data Bits 1–12. 14 DB0 Least Significant Data Bit (LSB). 15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if ...
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AD9754 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. ...
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Typical AC Characterization Curves (AVDD = +5 V, DVDD = + mA, 50 OUTFS otherwise noted) 90 25MSPS 5MSPS 80 65MSPS 70 125MSPS 60 50MSPS 100 f – MHz OUT Figure ...
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AD9754 1.0 0.5 0 –0.5 –1.0 –1.5 –2 12k 16k CODE Figure 12. Typical INL 1.0 0.5 0 –0.5 –1 12k 16k CODE Figure 13. Typical DNL 65MSPS CLOCK –10 f ...
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FUNCTIONAL DESCRIPTION Figure 16 shows a simplified block diagram of the AD9754. The AD9754 consists of a large PMOS current source array that is capable of providing total current. The array is divided into 31 ...
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AD9754 These last two equations highlight some of the advantages of operating the AD9754 differentially. First, the differential op- eration will help cancel common-mode error sources associated with IOUTA and IOUTB such as noise, distortion and dc off- sets. Second, ...
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REFIO is approximately simple, low cost R-2R ladder DAC configured in the voltage mode topology may be used to control the gain. This circuit is shown in Figure 19 using the AD7524 and ...
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AD9754 The most significant improvement in the AD9754’s distortion and noise performance is realized using a differential output configuration. The common-mode error sources of both IOUTA and IOUTB can be substantially reduced by the common-mode rejection of a transformer or ...
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INPUT CLOCK AND DATA TIMING RELATIONSHIP SNR in a DAC is dependent on the relationship between the position of the clock edges and the point in time at which the input data changes. The AD9754 is positive edge triggered, and ...
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AD9754 APPLYING THE AD9754 OUTPUT CONFIGURATIONS The following sections illustrate some typical output configura- tions for the AD9754. Unless otherwise noted assumed that I is set to a nominal 20 mA. For applications requir- OUTFS ing the optimum ...
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SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT Figure 30 shows the AD9754 configured to provide a unipolar output range of approximately +0.5 V for a doubly termi- nated 50 cable since the nominal full-scale current flows through ...
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AD9754 An example serves to illustrate the effect of supply noise on the analog supply. Suppose a switching regulator with a switching frequency of 250 kHz produces 10 mV rms of noise and for simplicity sake (i.e., ignore harmonics), all ...
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This particular multitone vector, has a peak-to-rms CLOCK ratio of 13.5 dB compared to a sine waves peak-to-rms ratio of 3 dB. A “snapshot” of this reconstructed multitone vector in the time domain as shown in Figure 34b ...
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AD9754 APPLICATIONS VDSL Applications Using the AD9754 Very High Frequency Digital Subscriber Line (VDSL) technol- ogy is growing rapidly in applications requiring data transfer over relatively short distances. By using QAM modulation and transmitting the data in multiple discrete tones, ...
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DVDD REFLO REFIO AD9754 (“I DAC”) U1 FSADJ DAC R SET1 2k LATCHES I DATA INPUT CLK AVDD REFLO LATCHES Q DATA U2 INPUT DAC AD9754 (“Q DAC”) REFIO FSADJ SLEEP R SET2 1.9k 0 CAL 220 ACOM ...
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AD9754 Figure 38. Evaluation Board Schematic –20– REV. A ...
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REV. A Figure 39. Silkscreen Layer—Top Figure 40. Component Side PCB Layout (Layer 1) –21– AD9754 ...
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AD9754 Figure 41. Ground Plane PCB Layout (Layer 2) Figure 42. Power Plane PCB Layout (Layer 3) –22– REV. A ...
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REV. A Figure 43. Solder Side PCB Layout (Layer 4) Figure 44. Silkscreen Layer—Bottom –23– AD9754 ...
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AD9754 0.0118 (0.30) 0.0040 (0.10) 0.006 (0.15) 0.002 (0.05) SEATING PLANE OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00 ...