AD9945KCP Analog Devices Inc, AD9945KCP Datasheet
AD9945KCP
Specifications of AD9945KCP
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AD9945KCP Summary of contents
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FEATURES 40 MSPS Correlated Double Sampler (CDS 10-Bit Variable Gain Amplifier (VGA) Low Noise Optical Black Clamp Circuit Preblanking Function 12-Bit 40 MSPS A/D Converter No Missing Codes Guaranteed 3-Wire Serial Digital Interface 3 V ...
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AD9945–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION Normal Operation (DRVDD Power not Included) DRVDD Power Only ( pF) LOAD Power-Down Mode MAXIMUM CLOCK RATE Specifications subject to change ...
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SYSTEM SPECIFICATIONS Parameter CDS Maximum Input Range before Saturation* Allowable CCD Reset Transient* Maximum CCD Black Pixel Amplitude* VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution Gain Monotonicity Gain Range Minimum Gain Maximum Gain Low Gain Mode BLACK LEVEL CLAMP Clamp ...
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AD9945 TIMING SPECIFICATIONS Parameter SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK High/Low Pulse Width SHP Pulse Width SHD Pulse Width CLPOB Pulse Width* SHP Rising Edge to SHD Falling Edge SHP Rising Edge to SHD Rising Edge Internal Clock ...
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Pin Number Mnemonic 1 to 10, 31 D11, D0 DRVDD 12 DRVSS 13 DVDD 14 DATACLK 15 DVSS 16 PBLK 17 CLPOB 18 SHP 19 SHD 20 AVDD 21 AVSS 22 CCDIN 23 REFT 24 ...
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AD9945 DEFINITIONS OF SPECIFICATIONS Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to ...
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150 V = 3.0 V 135 DD 120 105 SAMPLE RATE (MHz) TPC 1. Power vs. Sampling Rate REV. B Typical Performance Characteristics–AD9945 1.0 0.5 0 – 0.5 – 1.0 ...
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AD9945 INTERNAL REGISTER DESCRIPTION Register Address Bits Name Data Bits Operation D8, D7 D11 Control ...
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SERIAL INTERFACE SDATA SCK NOTES 1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK. 2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE. 3. ALL ...
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AD9945 DC RESTORE 0.1 F CCDIN CIRCUIT DESCRIPTION AND OPERATION The AD9945 signal processing chain is shown in Figure 6. Each processing step is essential in achieving a high quality image from the raw CCD pixel data. DC Restore To ...
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CCD MODE TIMING CCD SIGNAL SHP t S1 SHD DATACLK t OD OUTPUT N–10 DATA NOTES 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE. 2. ...
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AD9945 APPLICATIONS INFORMATION The AD9945 is a complete analog front end (AFE) product for digital still camera and camcorder applications. As shown in Figure 10, the CCD image (pixel) data is buffered and sent to the AD9945 analog input through ...
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Internal Power-On Reset Circuitry After power-on, the AD9945 will automatically reset all internal registers and perform internal calibration procedures. This takes approximately complete. During this time, normal clock signals and serial write operations may occur. However, serial ...
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... SEATING PLANE ORDERING GUIDE Model 1 Temperature Range AD9945KCPZ −20°C to +85°C AD9945KCPZRL7 −20°C to +85° RoHS Compliant Part. REVISION HISTORY 1/11—Rev Rev. B Changed 140 mW to 160 mW Throughout .................................. 1 Changes to Power Supply Voltage Parameter and Power Consumption, Normal Operation (DRVDD Power not Included) Parameter in General Specifications Table ...