EVAL-ADAU1446EBZ Analog Devices Inc, EVAL-ADAU1446EBZ Datasheet
EVAL-ADAU1446EBZ
Specifications of EVAL-ADAU1446EBZ
Related parts for EVAL-ADAU1446EBZ
EVAL-ADAU1446EBZ Summary of contents
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FEATURES Fully programmable audio digital signal processor (DSP) for enhanced sound processing Features SigmaStudio, a proprietary graphical programming tool for the development of custom signal flows 172 MHz SigmaDSP core; 3584 instructions per sample at 48 kHz 4k parameter RAM, ...
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ADAU1445/ADAU1446 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications ..................................................................................... 4 Digital Timing Specifications ..................................................... 6 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 ...
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GENERAL DESCRIPTION The ADAU1445/ADAU1446 are enhanced audio processors that allow full flexibility in routing all input and output signals. The SigmaDSP® core features full 28-bit processing (56-bit in double- precision mode), synchronous parameter loading for ensuring filter stability, and 100% ...
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ADAU1445/ADAU1446 SPECIFICATIONS AVDD = 3.3 V, DVDD = 1.8 V, PVDD = 3.3 V, IOVDD = 3 unless otherwise noted. Table 1. Parameter ANALOG PERFORMANCE Auxiliary Analog Inputs Resolution Full-Scale Analog Input Integral Nonlinearity (INL) Differential Nonlinearity (DNL) ...
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Parameter Maximum Digital Current (DVDD) of ADAU1445 Minimum Digital Current (DVDD) of ADAU1446 Maximum Digital Current (DVDD) of ADAU1446 Power Dissipation AVDD, DVDD, PVDD During Operation of ADAU1445 AVDD, DVDD, PVDD During Operation of ADAU1446 Reset, All Supplies TEMPERATURE RANGE ...
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ADAU1445/ADAU1446 DIGITAL TIMING SPECIFICATIONS T = −40°C to +105°C, DVDD = 1.8 V, IOVDD = 3 Table 2. 1 Parameter Min MASTER CLOCK f 2.822 MP t 40. CLKOUT Jitter CORE CLOCK f CORE ...
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Digital Timing Diagrams t BIH BCLKx INPUT t BIL t LIS LRCLKx INPUT t SIS SDATA_INx LEFT-JUSTIFIED MSB MODE t SIH SDATA_INx MODE SDATA_INx RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT ...
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ADAU1445/ADAU1446 t CLS t CLATCH CCPH CCLK CDATA t CDS COUT SDA SCL t MCLK RESET t CCPL t CDH Figure 4. SPI Port Timing SCH t t SCLR SCLH SCS SCLL SCLF 2 ...
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ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating DVDD to Ground 2.2 V AVDD to Ground 4.0 V IOVDD to Ground 4.0 V Digital Inputs DGND – 0 IOVDD + ...
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ADAU1445/ADAU1446 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 100 99 DGND 1 PIN 1 IOVDD 2 BCLK3 3 LRCLK3 4 SDATA_IN2 5 BCLK2 6 LRCLK2 7 SDATA_IN1 8 BCLK1 9 LRCLK1 10 SDATA_IN0 11 BCLK0 12 DGND 13 IOVDD 14 LRCLK0 15 ...
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Pin No. Mnemonic Type 1 6 BCLK2 D_IO 7 LRCLK2 D_IO 8 SDATA_IN1 D_IN 9 BCLK1 D_IO 10 LRCLK1 D_IO 11 SDATA_IN0 D_IN 12 BCLK0 D_IO 15 LRCLK0 D_IO 16 MP11 D_IO 17 MP10 D_IO 18 MP9 D_IO 19 MP8 ...
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ADAU1445/ADAU1446 Pin No. Mnemonic Type 1 34 MP6 D_IO 35 MP5 D_IO 36 MP4 D_IO 40 VDRIVE A_OUT 41 XTALO A_OUT 42 XTALI A_IN 43 PLL_FILT A_OUT 44 PVDD PWR 45 PGND PWR 46 SPDIFI D_IN 47 SPDIFO D_OUT 48 ...
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Pin No. Mnemonic Type 1 66 SDATA_OUT7 D_OUT 67 BCLK10 D_IO 68 LRCLK10 D_IO 69 SDATA_OUT6 D_OUT 70 BCLK9 D_IO 71 LRCLK9 D_IO 72 SDATA_OUT5 D_OUT 73 SDATA_IN8 D_IN 74 BCLK8 D_IO 78 LRCLK8 D_IO 79 SDATA_OUT4 D_OUT 80 SDATA_IN7 ...
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ADAU1445/ADAU1446 Pin No. Mnemonic Type 1 96 BCLK4 D_IO 97 LRCLK4 D_IO 98 SDATA_OUT0 D_OUT 99 SDATA_IN3 D_IN 1 PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_OUT = digital output, D_IO = ...
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THEORY OF OPERATION SYSTEM BLOCK DIAGRAM +3.3V VDRIVE ADAU1445/ ADAU1446 1.8V REGULATOR S/PDIF SPDIFI RECEIVER SDATA_IN[8:0] SERIAL DATA 9 INPUT PORT (24-CHANNEL (×9) DIGITAL AUDIO INPUT † BIT CLOCK (BCLK † FRAME CLOCK ...
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ADAU1445/ADAU1446 OVERVIEW The ADAU1445/ADAU1446 are each a 24-channel audio DSP with an integrated S/PDIF receiver and transmitter, flexible serial audio ports channels of asynchronous sample rate converters (ASRCs), flexible audio routing, and user interface capabilities. Signal processing ...
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Signal processing algorithms available in the provided libraries include • Single- and double-precision biquad filter • Mono and multichannel dynamics processors with peak or RMS detection • Mixer and splitter • Tone and noise generator • Fixed and variable gain ...
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ADAU1445/ADAU1446 INITIALIZATION Power-Up Sequence The ADAU1445/ADAU1446 have a built-in initialization period, which allows sufficient time for the PLL to lock and the registers to initialize their values positive edge of RESET , the PLL settings are immediately set ...
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... Short trace lengths in the oscillator circuit decrease stray capacitance, thereby increasing the loop gain of the circuit and helping to avoid crystal start-up problems. On the ADAU1445/ADAU1446 evaluation boards, the capac- itance value for C1 and pF. XTALO should not be used to directly drive the crystal signal to another IC ...
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ADAU1445/ADAU1446 Table 7. PLL Modes Input to MCLK DSP Core Rate 1 (XTALI Pin) Normal 64 × f S,NORMAL 128 × f S,NORMAL 256 × f S,NORMAL 384 × f S,NORMAL 512 × f S,NORMAL Dual 32 × f S,DUAL ...
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PLL Loop Filter The PLL loop filter should be connected to the PLL_FILT pin. This filter, shown in Figure 11, includes three passive components— two capacitors and a resistor. The values of these components do not need to be exact; ...
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ADAU1445/ADAU1446 Table 10. Bit Descriptions of Register 0xE220 Bit Position Description [15:5] Reserved [4:0] Start pulse select 00000 = internally generated normal rate (f 00001 = internally generated dual rate (f 00010 = internally generated quad rate (f 00011 = ...
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VOLTAGE REGULATOR The digital supply voltage of the ADAU1445/ADAU1446 must be set to 1.8 V. The chip includes an on-board voltage regulator that allows the device to be used in systems where a 1.8 V supply is not available but ...
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ADAU1445/ADAU1446 CONTROL PORT Overview The ADAU1445/ADAU1446 can operate in one of three control 2 modes control mode, SPI control mode, or self-boot mode (no external controller). The ADAU1445/ADAU1446 have both a 4-wire SPI control port 2 and a ...
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The R/ W bit determines the direction of the data. A Logic 0 on the LSB of the first byte means that the master writes information to the peripheral. A Logic 1 on the LSB of the ...
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ADAU1445/ADAU1446 SCL SDA START BY MASTER FRAME 1 CHIP ADDRESS BYTE SCL (CONTINUED) SDA (CONTINUED) FRAME 3 SUBADDRESS BYTE 2 SCL (CONTINUED) SDA (CONTINUED) FRAME 5 READ DATA BYTE 1 CHIP ADDRESS, SUBADDRESS R/W ...
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SPI Port By default, the ADAU1445/ADAU1446 are in I these parts can be put into SPI control mode by pulling CLATCH low three times. Each low pulse should have a minimum duration of 20 ns, and the delay between pulses ...
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ADAU1445/ADAU1446 Self-Boot On power-up, the ADAU1445/ADAU1446 can load a program and a set of parameters that are saved in an external EEPROM. Combined with the auxiliary ADC and the multipurpose pins, this can potentially eliminate the need for a microcontroller ...
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SERIAL DATA INPUT/OUTPUT The flexible serial data input and output ports of the ADAU1445/ ADAU1446 can be set to accept or transmit data in a 2-channel 2 (usually I S format), packed TDM4, or standard 4-, 8-, or 16- channel ...
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ADAU1445/ADAU1446 Table 17. Configurations for Standard Audio Data Formats Format LRCLK Polarity Frame begins on (Figure 22) falling edge Left-Justified Frame begins on (Figure 23) rising edge Right-Justified Frame begins on (Figure 24) rising edge TDM with ...
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Serial Audio Data Timing Diagrams Figure 22 to Figure 26 show timing diagrams for standard audio data formats. LRCLKx BCLKx SDATA_INx, MSB SDATA_OUTx LRCLKx LEFT CHANNEL BCLKx SDATA_INx, MSB SDATA_OUTx LRCLKx BCLKx SDATA_INx, MSB SDATA_OUTx LRCLKx BCLKx SDATA_INx, SDATA_OUTx LRCLKx ...
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ADAU1445/ADAU1446 Serial Clock Domains There are 12 clock domains (pairs of LRCLKx and BCLKx pins) available in the ADAU1445/ADAU1446. Of these, three are avail- able exclusively to the serial data input ports, three are available exclusively to the serial data ...
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Serial Clock Modes and Settings Dejitter Window Register (Address 0xE221) Table 19. Bit Descriptions of Register 0xE221 Bit Position Description [15:6] Reserved [5:0] Dejitter window 000000 = dejitter circuit bypass 000001 = minimum window … 111111 = maximum window Register ...
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ADAU1445/ADAU1446 Packed TDM4 Mode A special TDM mode is available that allows four channels to be fit into a space of 64 bit clock cycles. This mode is called packed TDM4 mode, or MOST™ mode. MOST (Media Oriented Systems Transport) ...
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SERIAL INPUT PORTS 2 The serial input ports convert standard I S and TDM signals into 16-, 20-, and 24-bit audio signals for input to the audio processor. They support TDM2, TDM4, TDM8, and TDM16 time division 2 multiplexing schemes ...
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ADAU1445/ADAU1446 SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN3 SDATA_IN4 SDATA_IN5 SDATA_IN6 SDATA_IN7 SDATA_IN8 DEDICATED INPUT CLOCK DOMAINS (×3) SERIAL INPUT PORTS (×9) CLOCK DOMAIN 18:2 SELECTOR (× 4:2 4:2 4:2 ...
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SERIAL INPUT PORT MODES AND SETTINGS Each of the nine serial input ports is controlled by setting an individual 2-byte word in the serial input mode register for each port (see Table 23 for the register addresses). Each serial data ...
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ADAU1445/ADAU1446 Bit Position Description [7:6] Word length bits bits bits 11 = flexible TDM mode [5:3] MSB position 2 000 = I S (delayed by 1) 001 = left justified (delayed ...
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BCLK POLARITY LRCLKx BCLKx SDATA_INx LRCLKx BCLKx SDATA_INx LRCLK POLARITY LRCLKx LRCLKx Word Length Bits (Bits[7:6]) These bits set the word length of the input data to 16, 20 bits. If the input signal has more data bits ...
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ADAU1445/ADAU1446 selector (that is, the 18:2 multiplexer) allows each serial output port to clock from any available clock domain. In master mode, the clock domain selector is bypassed, and the assignments described in Table 26 are used. Table 26. Output ...
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Serial Output Port Modes Registers (Address 0xE040 to Address 0xE049) Table 27. Addresses of Serial Output Port Modes Registers Address Decimal Hex Name 57408 E040 Serial Output Port 0 modes 57409 E041 Serial Output Port 1 modes 57410 E042 Serial ...
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ADAU1445/ADAU1446 Table 28. Bit Descriptions of Serial Output Port Modes Registers Bit Position Description [15] Clock output enable 0 = LRCLK and BCLK output pins disabled 1 = LRCLK and BCLK output pins enabled [14] Frame sync type 0 = ...
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Clock Output Enable Bit (Bit 15) This bit controls the serial port’s respective bit clock as well as the left and right clocks. When this bit is set to 1, the clock pins are set to output. When this bit ...
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ADAU1445/ADAU1446 FLEXIBLE AUDIO ROUTING MATRIX (FARM) The routing matrix distributes audio signals among the serial inputs, serial outputs, ASRCs, S/PDIF receiver and transmitter, and DSP core. This simplifies the design of complex systems that require many inputs and outputs with ...
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Routing Matrix Functionality Serial Input Ports The far left side of Figure 36 represents the audio input pins to the ADAU1445/ADAU1446, namely SDATA_IN0 to SDATA_IN8 and SPDIFI. The serial audio data signals can be represented in any standard mode, including ...
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ADAU1445/ADAU1446 Flexible Audio Routing Matrix—Input Side Up until this point in the audio signal flow, all signals can be asynchronous to each other. However, before entering the DSP for processing, the signals must be synchronized to the same clock. Therefore, ...
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Stereo ASRC Routing Overview Within the ADAU1445, signals are required to be synchronous to the master clock only when they are within the DSP core itself. At all other times, signals can be asynchronous to one another and the core. ...
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ADAU1445/ADAU1446 Sample Rate Conversion Before the DSP If asynchronous input signals are present in the system, they must be routed through the ASRC before being processed by the DSP. This is made possible by routing the asynchronous signals through the ...
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Flexible Audio Routing Matrix—Output Side Much like the input side, the output side of the flexible audio routing matrix takes several stereo pairs, which can be asynchro- nous, and connects them to the 12 stereo pairs that are output from ...
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ADAU1445/ADAU1446 OUTPUT CHANNELS (24 CH 10, 11 12, 13 14, 15 16, 17 18, 19 20, 21 22, 23 FLEXIBLE AUDIO ROUTING MATRIX MODES AND SETTINGS Table 30. Addresses of ...
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ASRC Input Select Pairs[7:0] Registers (Address 0xE080 to Address 0xE087) The inputs to each of the eight ASRCs can come from any stereo pair from either the serial input channels or the DSP core. In the case of the ADAU1445, ...
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ADAU1445/ADAU1446 ASRC Input Data Selector Bits (Bits[5:0]) As shown in Figure 49, the gray box representing the input side of the flexible audio routing matrix can be thought multiplexer. Any input to the box can make a ...
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ASRC Output Rate Select Pairs[7:0] Registers (Address 0xE088 to Address 0xE08F) Table 32. Bit Descriptions of ASRC Output Rate Select Pairs[7:0] Registers Bit Position Description [15:6] Reserved [5:0] ASRC output rate 000000 = Serial Output Pair 0 (Channel 0, Channel ...
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ADAU1445/ADAU1446 Serial Output Select Pairs[11:0] Registers (Address 0xE090 to Address 0xE09B) Table 33. Bit Descriptions of Serial Output Select Pairs[11:0] Registers Bit Position Description [15:6] Reserved [5:0] Serial output data selector 010000 = DSP Output Pair 0 (Channel 0, Channel ...
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Serial Output Data Selector Bits (Bits[5:0]) These bits select where each of the 12 stereo serial output channels comes from. The channels can come either from one of the 12 DSP core stereo outputs or from one of the eight ...
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ADAU1445/ADAU1446 ASYNCHRONOUS SAMPLE RATE CONVERTERS The integrated sample rate converters of the ADAU1445/ ADAU1446 processors can be configured in various ways to facilitate asynchronous connectivity to other components in the audio system. The sample rate converters operate completely independent of ...
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The muting is done with a volume ramp and is click and pop free. If desired, the mute ramp can be disabled for Stereo ASRC[7:4] (see the Stereo ASRC[7:4] Mute Ramp Disable Register (Address 0xE143) section). In the case of ...
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ADAU1445/ADAU1446 DSP CORE The DSP core performs calculations on audio data as specified by the instruction codes stored in program RAM. Because SigmaStudio generates the instructions not necessary to have a detailed knowledge of the DSP core to ...
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Numeric Formats DSP systems commonly use a standard numeric format. Fractional number systems are specified by an A.B format, where A is the number of bits to the left of the decimal point and B is the number of bits ...
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ADAU1445/ADAU1446 RELIABILITY FEATURES The ADAU1445/ADAU1446 contain several subsystems designed to increase the reliability of the system in which they are used. When these functions are used in conjunction with an external host controller device, the DSP can recover from serious ...
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Watchdog Modes and Settings Watchdog Registers (Address 0xE210 to Address 0xE212) Table 42. Register Details of Watchdog Registers Address Decimal Hex Register 57872 E210 Watchdog enable 57873 E211 Watchdog Value 1 57874 E212 Watchdog Value 2 A program counter watchdog ...
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ADAU1445/ADAU1446 RAMS The ADAU1445/ADAU1446 have 4k words of program RAM, 4k words of parameter RAM, and 8k words of data RAM. Program RAM Table 46. Register Details of Program RAM Address Decimal Hex Name 8192 2000 Program RAM The program ...
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S/PDIF RECEIVER AND TRANSMITTER The ADAU1445/ADAU1446 each feature a set of on-chip S/PDIF data ports, which can be wired directly to transmitters and receivers for easy interfacing to other S/PDIF-compatible equipment. S/PDIF Receiver The S/PDIF input port is designed to ...
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ADAU1445/ADAU1446 S/PDIF MODES AND SETTINGS Table 52. Addresses of S/PDIF Modes Registers Address Decimal Hex Name 57536 E0C0 S/PDIF receiver—read auxiliary output 57537 E0C1 S/PDIF transmitter— on/off switch 57538 E0C2 S/PDIF read channel status, Byte 0 57539 E0C3 S/PDIF read ...
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Auxiliary Outputs—Set Enable Mode Register (Address 0xE0C8) Table 57. Bit Descriptions of Register 0xE0C8 Bit Position Description [15:2] Reserved [1:0] Word length 00 = auxiliary outputs are always off auxiliary outputs are always on auxiliary outputs ...
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ADAU1445/ADAU1446 2 Enable S/PDIF Output Register (Address 0xE241) Table 62. Bit Descriptions of Register 0xE241 Bit Position Description [15:3] Reserved [2] Output mode TDM [1] Group 2 enable 0 = ...
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MULTIPURPOSE PINS The ADAU1445/ADAU1446 each include 12 multipurpose pins that can be used either as digital general-purpose inputs/outputs (GPIOs inputs to the 4-channel auxiliary ADC. Each of the 12 multipurpose pins is controlled by a 4-bit mode. Pins ...
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ADAU1445/ADAU1446 AUXILIARY ADC The ADAU1445/ADAU1446 include a 10-bit auxiliary ADC that can be used for control input signals. There is one ADC with four multiplexed inputs. The ADC samples at a rate of f (192 kHz when based on a ...
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INTERFACING WITH OTHER DEVICES When interfacing the ADAU1445/ADAU1446 to other devices in the system, it may be necessary to set the drive strength of each pin. DRIVE STRENGTH MODES AND SETTINGS Bit Clock Pad Strength Register (Address 0xE247) This register ...
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ADAU1445/ADAU1446 Frame Clock Pad Strength Register (Address 0xE248) This register controls the pad drive strength of all frame clock pins configured in master mode. The default 2 mA setting should be adequate for most applications. The 6 mA setting should ...
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Multipurpose Pin Pad Strength Register (Address 0xE249) This register controls the pad drive strength of all multipurpose pins configured as outputs. The default 2 mA setting should be adequate for most applications. The 6 mA setting should be used only ...
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ADAU1445/ADAU1446 Serial Data Output Pad Strength Register (Address 0xE24A) This register controls the pad drive strength of all serial data output pins. The default 2 mA setting should be adequate for most applications. The 6 mA setting should be used ...
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Other Pad Strength Register (Address 0xE24C) This register controls the pad drive strength of the communications port, S/PDIF output, and master clock outputs. The default 2 mA setting should be adequate for most applications. The 6 mA setting should be ...
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... Each of the 24 input channels is capable of taking data from any slot (or combination of slots) in the flexible TDM stream, as long as data retrieval starts with Input Channel 0 and increases sequentially. Because the audio data can be input in 8-, 16-, or 24-bit format, LRCLKx ...
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Flexible TDM to Input Channel Modes Registers (Address 0xE180 to Address 0xE197) Table 73. Addresses of Serial Input Flexible TDM Interface Modes Registers Address Decimal Hex Name 57728 E180 Flexible TDM to Input Channel 0 57729 E181 Flexible TDM to ...
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... TDM stream. Each of the 64 TDM output slots is capable of taking its data from any of these 24 output channels, as long as data retrieval starts with Output Channel 0 and increases sequentially. Because the audio data can be input in 8-, 16-, or 24-bit formats, a single channel of audio data may occupy more than one slot ...
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OUTPUT CHANNELS (24 CH) ... SDATA_OUT0 ...
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ADAU1445/ADAU1446 Address Decimal Hex Name 57821 E1DD TDM Slot 58 and TDM Slot 59 (SDATA_OUT1) 57822 E1DE TDM Slot 60 and TDM Slot 61 (SDATA_OUT1) 57823 E1DF TDM Slot 62 and TDM Slot 63 (SDATA_OUT1) 1 Slot 31 and Slot ...
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SOFTWARE FEATURES SOFTWARE SAFELOAD To update parameters in real time while avoiding pop and click noises on the output, the ADAU1445/ADAU1446 use a software safeload mechanism. SigmaStudio sets up the necessary code and parameters automatically for new projects. The safeload ...
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ADAU1445/ADAU1446 GLOBAL RAM AND REGISTER MAP This section contains a list of all RAMS and registers. OVERVIEW OF REGISTER ADDRESS MAP Table 79. ADAU1445/ADAU1446 RAM and Register Map Address Decimal Start Value End Value Start Value 0 4095 0000 8192 ...
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Table 83. Serial Input Port Modes Registers Address Decimal Hex 57344 E000 57345 E001 57346 E002 57347 E003 57348 E004 57349 E005 57350 E006 57351 E007 57352 E008 Table 84. Serial Output Port Modes Registers Address Decimal Hex Name 57408 ...
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ADAU1445/ADAU1446 Address Decimal Hex Name 57491 E093 Serial output select, Pair 3 (Channel 6, Channel 7) 57492 E094 Serial output select, Pair 4 (Channel 8, Channel 9) 57493 E095 Serial output select, Pair 5 (Channel 10, Channel 11) 57494 E096 ...
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Address Decimal Hex Name 57736 E188 Flexible TDM to Input Channel 8 57737 E189 Flexible TDM to Input Channel 9 57738 E18A Flexible TDM to Input Channel 10 57739 E18B Flexible TDM to Input Channel 11 57740 E18C Flexible TDM ...
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ADAU1445/ADAU1446 Address Decimal Hex Name 57821 E1DD TDM Slot 58 and TDM Slot 59 (SDATA_OUT1) 57822 E1DE TDM Slot 60 and TDM Slot 61 (SDATA_OUT1) 57823 E1DF TDM Slot 62 and TDM Slot 63 (SDATA_OUT1) Table 90. Other Modes Registers ...
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APPLICATIONS INFORMATION LAYOUT RECOMMENDATIONS Parts Placement All 100 nF bypass capacitors, which are recommended for every analog, digital, and PLL power-ground pair, should be placed as close to the ADAU1445/ADAU1446 as possible. The AVDD, DVDD, PVDD, and IOVDD supply signals ...
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ADAU1445/ADAU1446 100nF IOVDD DGND 1 100nF 2 IOVDD IOVDD 13 DGND 100nF 14 IOVDD DVDD DVDD 100nF BULK BYPASS ...
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TYPICAL APPLICATION SCHEMATICS 100nF IOVDD 100nF IOVDD 100nF SELF-BOOT MEMORY D3V3 D3V3 VCC 2.2kΩ 2.2kΩ SCL 4 5 GND SDA 24AA256 100nF BULK BYPASS CAPACITORS D3V3 AVDD PVDD IOVDD + ...
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ADAU1445/ADAU1446 100nF IOVDD DGND 1 100nF 2 IOVDD 3 BCLK3 4 LRCLK3 5 SDATA_IN2 6 BCLK2 7 LRCLK2 8 SDATA_IN1 9 BCLK1 10 LRCLK1 11 SDATA_IN0 12 BCLK0 IOVDD 13 DGND 100nF 14 IOVDD 15 LRCLK0 16 MP11 17 MP10 ...
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DVDD 100nF IOVDD 1 DGND 100nF 2 IOVDD 3 BCLK3 4 LRCLK3 5 SDATA_IN2 6 BCLK2 7 LRCLK2 8 SDATA_IN1 9 BCLK1 10 LRCLK1 11 SDATA_IN0 12 BCLK0 IOVDD 13 DGND 100nF 14 IOVDD 15 LRCLK0 16 MP11 17 MP10 ...
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... Temperature Range 1 ADAU1445YSVZ-3A −40°C to +105°C ADAU1445YSVZ-3A-RL 1 −40°C to +105°C 1 ADAU1446YSTZ-3A −40°C to +105°C 1 ADAU1446YSTZ-3A-RL −40°C to +105°C 1 EVAL-ADAU1442EBZ 1 EVAL-ADAU1446EBZ RoHS Compliant Part. 1.20 16.00 BSC SQ MAX 14.00 BSC SQ 76 100 1 75 PIN 1 TOP VIEW (PINS DOWN ...
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NOTES Rev Page ADAU1445/ADAU1446 ...
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ADAU1445/ADAU1446 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, ...