ADC12034 National Semiconductor Corporation, ADC12034 Datasheet

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ADC12034

Manufacturer Part Number
ADC12034
Description
Self-calibrating 12-bit Plus Sign Serial I/o A/d Converters With Mux And Sample/hold
Manufacturer
National Semiconductor Corporation
Datasheet

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© 2007 National Semiconductor Corporation
ADC12H030/ADC12H032/ADC12H034/ADC12H038,
ADC12030/ADC12032/ADC12034/ADC12038
Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters
with MUX and Sample/Hold
General Description
Some device/package combinations are obsolete and
shown for reference only.
The ADC12030, and ADC12H030 families are 12-bit plus sign
successive approximation A/D converters with serial I/O and
configurable input multiplexers. The ADC12034/ADC12H034
and ADC12038/ADC12H038 have 4 and 8 channel multiplex-
ers, respectively. The differential multiplexer outputs and A/D
inputs are available on the MUXOUT1, MUXOUT2, A/DIN1
and A/DIN2 pins. The ADC12030/ADC12H030 has a two
channel multiplexer with the multiplexer outputs and A/D in-
puts internally connected. The ADC12030 family is tested
with a 5 MHz clock, while the ADC12H030 family is tested
with an 8 MHz clock. On request, these A/Ds go through a
self calibration process that adjusts linearity, zero and full-
scale errors to less than ±1 LSB each.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or pseudo-differ-
ential modes. A fully differential unipolar analog input range
(0V to +5V) can be accommodated with a single +5V supply.
In the differential modes, valid outputs are obtained even
when the negative inputs are greater than the positive be-
cause of the 12-bit plus sign output data format.
The serial I/O is configured to comply with NSC MICROWIRE.
For voltage references see the LM4040, LM4050 or LM4041.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
11354
Features
Key Specifications
Applications
Serial I/O (MICROWIRE Compatible)
2, 4, or 8 chan differential or single-ended multiplexer
Analog input sample/hold function
Power down mode
Variable resolution and conversion rate
Programmable acquisition time
Variable digital output word length and format
No zero or full scale adjustment required
Fully tested and guaranteed with a 4.096V reference
0V to 5V analog input range with single 5V power supply
No Missing Codes over temperature
Medical instruments
Process control systems
Test equipment
Resolution
12-bit plus sign conversion time
– ADC12H30 family
– ADC12030 family
12-bit plus sign throughput time
– ADC12H30 family
– ADC12030 family
Integral Linearity Error
Single Supply
Power consumption
– Power down
12-bit plus sign
±1 LSB (max)
33 mW (max)
100 µW (typ)
5.5 µs (max)
8.8 µs (max)
8.6 µs (max)
www.national.com
14 µs (max)
5V ±10%
April 2007

Related parts for ADC12034

ADC12034 Summary of contents

Page 1

... The ADC12030, and ADC12H030 families are 12-bit plus sign successive approximation A/D converters with serial I/O and configurable input multiplexers. The ADC12034/ADC12H034 and ADC12038/ADC12H038 have 4 and 8 channel multiplex- ers, respectively. The differential multiplexer outputs and A/D inputs are available on the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 pins ...

Page 2

ADC12038 Simplified Block Diagram Connection Diagrams 16-Pin Wide Body SO Packages Top View www.national.com 1135406 2 1135401 20-Pin Wide Body SO Packages 1135407 Top View ...

Page 3

... Ordering Information Industrial Temperature Range ≤ −40°C ADC12H030CIWM, ADC12030CIWM ADC12030CIWMX ADC12032CIWM ADC12034CIN ADC12034CIWM ADC12H034CIMSA ADC12H034CIMSAX ADC12H038CIWM, ADC12038CIWM ADC12H038CIWMX, ADC12038CIWMX * Some of these product/package combinations are on lifetime buy or are obsolete and shown here for reference only. Check our web site for product/package availability. ...

Page 4

Pin Descriptions CCLK The clock applied to this input con- trols the successive approximation conversion time interval and the ac- quisition time. The rise and fall times of the clock edges should not exceed 1 µs. SCLK This is the ...

Page 5

CH0–CH7 These are the analog inputs of the MUX. A channel input is selected by the address information at the DI pin, which is loaded on the rising edge of SCLK into the address register (See Tables 2, 3, 4). ...

Page 6

... Vapor Phase (60 seconds) Infrared (15 seconds) Storage Temperature Converter Electrical Characteristics The following specifications apply for V mode MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038 ADC12032, ADC12034 and ADC12038, R 2.048V common-mode voltage, and 10(t ; all other limits MIN MAX A J ...

Page 7

Symbol Parameter TUE Total Unadjusted Error Multiplexer Chan-to-Chan Matching Power Supply Sensitivity Offset Error + Full-Scale Error − Full-Scale Error Integral Linearity Error Output Data from “12-Bit Conversion of Offset” Output Data from “12-Bit Conversion of Full-Scale” UNIPOLAR DYNAMIC CONVERTER ...

Page 8

... AC Electrical Characteristics The following specifications apply for V mode ns MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038 ADC12030, ADC12032, ADC12034 and ADC12038, R input with fixed 2.048V common-mode voltage, and 10 all other limits MIN MAX ...

Page 9

... Timing Characteristics The following specifications apply for V mode ns MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H03 ADC12030, ADC12032, ADC12034 and ADC12038, R input with fixed 2.048V common-mode voltage, and 10 all other limits MIN MAX ...

Page 10

Symbol Parameter t Delay from SCLK Falling Edge to CS Falling Edge DELAY Delay from CS Rising Edge to DO TRI-STATE Hold Time from Serial Data Clock Rising Edge HDI t DI Set-Up ...

Page 11

Note 17: Timing specifications are tested at the TTL logic levels 1.4V. Note 18: The ADC12030 family's self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in a maximum ...

Page 12

FIGURE 3. Simplified Error Curve vs. Output Code after Auto-Calibration Cycle www.national.com FIGURE 4. Offset or Zero Error Voltage 12 1135412 1135413 ...

Page 13

Typical Performance Characteristics calibration unless otherwise specified. The performance for 8-bit + sign mode is equal to or better than shown. (Note 9) Linearity Error Change vs. Clock Frequency Linearity Error Change vs. Reference Voltage Full-Scale Error Change vs. Clock ...

Page 14

Full-Scale Error Change vs. Reference Voltage Zero Error Change vs. Clock Frequency Zero Error Change vs. Reference Voltage www.national.com Full-Scale Error Change vs. Supply Voltage 1135459 Zero Error Change 1135461 Zero Error Change vs. Supply Voltage 1135463 14 1135460 vs. ...

Page 15

Analog Supply Current vs. Temperature 1135465 Digital Supply Current vs. Temperature 1135467 Digital Supply Current vs. Clock Frequency 15 1135466 www.national.com ...

Page 16

Typical Dynamic Performance Characteristics after auto-calibration unless otherwise specified. Bipolar Spectral Response with 1 kHz Sine Wave Input Bipolar Spectral Response with 20 kHz Sine Wave Input Bipolar Spectral Response with 40 kHz Sine Wave Input www.national.com The following curves ...

Page 17

Bipolar Spurious Free Dynamic Range 1135474 Unipolar Signal-to-Noise + Distortion Ratio vs. Input Frequency 1135476 Unipolar Spectral Response with 1 kHz Sine Wave Input 1135478 Unipolar Signal-to-Noise Ratio vs. Input Frequency Unipolar Signal-to-Noise + Distortion Ratio vs. Input Signal Level ...

Page 18

Unipolar Spectral Response with 20 kHz Sine Wave Input Unipolar Spectral Response with 40 kHz Sine Wave Input www.national.com Unipolar Spectral Response with 30 kHz Sine Wave Input 1135480 Unipolar Spectral Response with 50 kHz Sine Wave Input 1135482 18 ...

Page 19

Test Circuits DO “TRI-STATE” Timing Diagrams DO Falling and Rising Edge , 1135403 Leakage Current DO “TRI-STATE” Falling and Rising Edge 1135418 DI Data Input Timing 19 DO except “TRI-STATE” 1135404 1135405 1135419 1135420 www.national.com ...

Page 20

Note: DO output data is not valid during this cycle. www.national.com DO Data Output Timing Using CS DO Data Output Timing with CS Continuously Low ADC12038 Auto Cal or Auto Zero 20 1135421 1135422 1135423 ...

Page 21

ADC12038 Read Data without Starting a Conversion Using CS ADC12038 Read Data without Starting a Conversion with CS Continuously Low 21 1135424 1135425 www.national.com ...

Page 22

ADC12038 Conversion Using CS with 8-Bit Digital Output Format ADC12038 Conversion Using CS with 16-Bit Digital Output Format www.national.com 22 1135426 1135451 ...

Page 23

ADC12038 Conversion with CS Continuously Low and 8-Bit Digital Output Format ADC12038 Conversion with CS Continuously Low and 16-Bit Digital Output Format 23 1135428 1135429 www.national.com ...

Page 24

ADC12038 Software Power Up/Down Using CS with 16-Bit Digital Output Format ADC12038 Software Power Up/Down with CS Continuously Low and 16-Bit Digital Output Format www.national.com 24 1135452 1135431 ...

Page 25

Note: Hardware power up/down may occur at any time high while a conversion is in progress that conversion will be corrupted and erroneous data will be stored in the output shift register. ADC12038 Configuration Modification—Example of a ...

Page 26

Ceramic or better FIGURE 5. Recommended Power Supply Bypassing and Grounding FIGURE 6. Protecting the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 Analog Pins www.national.com 1135434 26 1135435 ...

Page 27

Format and Set-Up Tables DO Formats DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB1 Bits MSB 13 Sign MSB 10 First Bits 9 Sign MSB 6 Bits with Sign 17 LSB 1 2 ...

Page 28

... TABLE 2. ADC12038 Multiplexer Addressing and Assignment A/DIN1 A/DIN2 MUXOUT M − − + − − + − + − − − + − + − − + − + − + TABLE 3. ADC12034 Multiplexer Addressing A/D Input Polarity Assignment CH2 CH3 COM A/DIN1 A/DIN2 + − − − − + − + − − + − ...

Page 29

... Note: ADC12030 and ADC12H030 do not have A/DIN1, A/DIN2, MUX- OUT1 and MUXOUT2 pins. ADC12038 DI0 DI1 DI2 DI3 ADC12034 DI0 DI1 DI2 ADC12030 and DI0 DI1 ADC12032 See Tables Table 4 See Tables Table 4 See Tables Table 4 L ...

Page 30

Status Bit DB0 DB1 Location Status Bit PU PD Device Status “High” “High” indicates a indicates a Power Up Power Sequence Down is in Sequence Function progress is in progress www.national.com TABLE 7. Status Register DB2 DB3 DB4 Cal 8 ...

Page 31

Applications Information Some of the device/package combinations are obsolete and are described here for reference only. Please see our web site for availability. 1.0 DIGITAL INTERFACE 1.1 Interface Concepts The example in Figure 7 shows a typical sequence of events ...

Page 32

... ADC12H032 ADC12032 ADC12H034 ADC12034 ADC12H038 ADC12038 Where X can be a logic high (H) or low (L). FIGURE 8. Changing the ADC's Conversion Configuration 1.6 User Mode and Test Mode An instruction may be issued to the ADC to put it into test mode, which is used by the manufacturer to verify complete functionality of the device. During test mode CH0– ...

Page 33

Reading the Data Without Starting a Conversion The data from a particular conversion may be accessed with- out starting a new conversion by ensuring that the CONV line is taken high during the I/O sequence. See the Read Data ...

Page 34

For pseudo-differential signed operation, the biasing circuit shown in Figure 12 shows a signal AC coupled to the ADC. This gives a digital output range of −4096 to +4095. With a 2.5V reference, 1 LSB is equal to 610 µV. ...

Page 35

FIGURE 13. Alternative Pseudo-Differential Biasing FIGURE 14. Pseudo-Differential Biasing without the Loss of Digital Output Range 35 1135448 1135449 www.national.com ...

Page 36

REFERENCE VOLTAGE The difference in the voltages applied to the V − defines the analog input span (the difference between the voltage applied between two multiplexer inputs or the voltage applied to one of the multiplexer inputs and analog ...

Page 37

FIGURE 17. V Operating Range REF 4.0 ANALOG INPUT VOLTAGE RANGE The ADC12030/2/4/8's fully differential ADC generate a two's complement output that is found by using the equations shown below: for (12-bit) resolution the Output Code = for (8-bit) resolution ...

Page 38

CLOCK SIGNAL LINE ISOLATION The ADC12030/2/4/8's performance is optimized by routing the analog input/output and reference signal conductors as far as possible ...

Page 39

A sample program, written in Microsoft QuickBasic, is shown on the next page. The program prompts for data mode select instruction to be sent to the A/D. This can be found from the Mode Programming table shown earlier. The data ...

Page 40

DOL=Data Out word length, DI=Data string for A/D DI input, ' DO=A/D result string 'SET CS# HIGH OUT &H3FC, (&H2 OR INP (&H3FC)) OUT &H3FC, (&HFE AND INP(&H3FC)) OUT &H3FC, (&HFD AND INP(&H3FC)) OUT &H3FC, (&HEF AND INP(&H3FC)) 10 ...

Page 41

Physical Dimensions inches (millimeters) unless otherwise noted Order Number ADC12030CIWM or ADC12H030CIWM NS Package Number M16B Order Number ADC12032CIWM NS Package Number M20B 41 www.national.com ...

Page 42

... Order Number ADC12034CIWM NS Package Number M24B Order Number ADC12H034CIMSA NS Package Number MSA24 42 ...

Page 43

... Order Number ADC12038CIWM or ADC12H038CIWM NS Package Number M28B Order Number ADC12034CIN NS Package Number N24C 43 www.national.com ...

Page 44

... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...

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