ADG738 Analog Devices, ADG738 Datasheet
ADG738
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ADG738 Summary of contents
Page 1
... On resistance is closely matched between switches and very flat over the full signal range. The ADG738 and ADG739 utilize a 3-wire serial interface that is compatible with SPI™, QSPI™, MICROWIRE™, and some DSP interface standards. The output of the shift register DOUT enables a number of these parts to be daisy-chained ...
Page 2
... ADG739 C (OFF (OFF) D ADG738 ADG739 (ON ADG738 ADG739 POWER REQUIREMENTS I DD NOTES 1 Temperature range is as follows: B Version: –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice 10%, GND = 0 V, unless otherwise noted.) ...
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... MHz typ 100 MHz typ 13 pF typ 85 pF typ 42 pF typ 96 pF typ 48 pF typ µA typ 10 µA max 20 ADG738/ADG739 Test Conditions/Comments mA Test Circuit ...
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... ADG738/ADG739 TIMING CHARACTERISTICS Parameter Limit MIN MAX f 30 SCLK 4 NOTES 1 See Figure 1. 2 All input signals are specified with (10 kΩ. ...
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... Scale) (Not to Scale S3A S4A ORDERING GUIDE Package Description Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) ADG738/ADG739 16 DOUT 15 GND S1B 12 S2B 11 S3B 10 S4B 9 DB Package Option RU-16 RU-16 ...
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... Peak Current 100 mA (Pulsed at 1 ms, 10% Duty Cycle max) Continuous Current, Each Continuous Current D, ADG739 . . . . . . . . . . . . . . . . . 80 mA Continuous Current D, ADG738 . . . . . . . . . . . . . . . . 120 mA Operating Temperature Range Industrial (B Version –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C CAUTION ESD (electrostatic discharge) sensitive device ...
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... Typical Performance Characteristics–ADG738/ADG739 DRAIN OR SOURCE VOLTAGE – 0. 0. (ON) D 0.04 0.00 I (OFF) S –0.04 I (OFF) D –0.08 –0. – Volts ...
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... OFF OFF DD 0 –40 – TEMPERATURE – ADG738 –5 ADG739 –10 –15 –20 30k 100k 1M 10M 100M FREQUENCY – –20 –40 –60 –80 –100 –120 30k 100k ...
Page 9
... SBUF register is arranged correctly as the switch expects MSB first. When data transmitted to the Matrix Switch, P3.3 is taken low. Data on RXD is clocked out of the microcontroller on the rising edge of TXD and is valid on the falling edge result no glue logic is required between the ADG738/ADG739 and microcontroller interface. 80C51/80L51* DB0 (LSB) S2 ...
Page 10
... If more devices need to be addressed via one chip select line, the ADG738 is an 8-channel device and would allow further expansion of the chip select scheme. There may be some digital feedthrough from the digital input lines because SCLK and DIN are permanently connected to each device ...
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... INPUT LOGIC * SIMILAR CONNECTION FOR ADG739 TEST CIRCUITS D (OFF SYNC 50% 50 OUT 90% t OFF SYNC D SWITCH OFF V OUT C L 1nF GND ADG738/ADG739 (OFF GND (ON GND ...
Page 12
... PIN 1 0.006 (0.15) 0.0433 (1.10) MAX 0.002 (0.05 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) BSC 0.0075 (0.19) PLANE 0.0035 (0.090 ADG738 OUT R L GND OUT S V WITH SWITCH OUT 10 V WITHOUT SWITCH OUT 0.028 (0.70) 0.020 (0.50) ...