ADSP-2185N Analog Devices, ADSP-2185N Datasheet

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ADSP-2185N

Manufacturer Part Number
ADSP-2185N
Description
16-BIT DIGITAL SIGNAL PROCESSOR
Manufacturer
Analog Devices
Datasheet

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PERFORMANCE FEATURES
12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sus-
Single-cycle instruction execution
Single-cycle context switch
3-bus architecture allows dual operand fetches in every
Multifunction instructions
Power-down mode featuring low CMOS standby power dissi-
Low power dissipation in idle mode
INTEGRATION FEATURES
ADSP-2100 family code compatible (easy to use algebraic
Up to 256K byte of on-chip RAM, configured
Dual-purpose program memory for both instruction and
Independent ALU, multiplier/accumulator, and barrel shifter
Two independent data address generators
Powerful program sequencer provides zero overhead loop-
Programmable 16-bit interval timer with prescaler
100-lead LQFP and 144-ball BGA
ICE-Port is a trademark of Analog Devices, Inc.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
a
tained performance
instruction cycle
pation with 200 CLKIN cycle recovery from power-down
condition
syntax), with instruction set extensions
Up to 48K words program memory RAM
Up to 56K words data memory RAM
data storage
computational units
ing conditional instruction execution
D A T A A D D RES S
G ENERAT OR S
D A G1
A LU
A R ITH M ETIC UN ITS
A DS P-2100 B AS E
A RC H IT EC T UR E
D AG2
MAC
SEQ U ENCER
PROG RAM
S H IFTE R
P R O GR A M M EM O R Y AD D R ES S
PR O GRAM M EMO R Y DATA
D ATA M EM O RY A D D R ES S
Figure 1. Functional Block Diagram
DA TA M E M OR Y DA TA
48K
PRO GRA M
ME M ORY
U P T O
24-B IT
S POR T0
PO W E R-DO WN
S ER IAL PO R TS
M EM OR Y
C ONTR O L
56K
SPOR T 1
ME M ORY
U P T O
D A TA
16-B IT
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
SYSTEM INTERFACE FEATURES
Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation
16-bit internal DMA port for high-speed access to on-chip
4M-byte memory interface for storage of data tables and pro-
8-bit DMA to byte memory for transparent program and data
Programmable memory strobe and separate I/O memory
Programmable wait state generation
Two double-buffered serial ports with companding hardware
Automatic booting of on-chip program memory from byte-
Six external interrupts
13 programmable flag pins provide flexible system signaling
UART emulation through software SPORT reconfiguration
ICE-Port™ emulator interface supports debugging in final
All inputs tolerate up to 3.6 V regardless of mode
memory (mode selectable)
gram overlays (mode selectable)
memory transfers (mode selectable)
space permits “glueless” system design
and automatic data buffering
wide external memory, for example, EPROM, or through
internal DMA Port
systems
T IM ER
PROG RA MM ABL E
F LA GS
A N D
I/O
© 2006 Analog Devices, Inc. All rights reserved.
DSP Microcomputer
ADSP-218xN Series
FU L L M EM O R Y M O D E
C ON T R OLL ER
H OS T M OD E
EX TE RNAL
EX TE RNAL
EX TE RNAL
BY TE DM A
INTER NA L
AD D R ES S
D A TA
D A TA
P ORT
OR
B U S
B U S
B U S
D M A
www.analog.com

Related parts for ADSP-2185N

ADSP-2185N Summary of contents

Page 1

... CLKIN cycle recovery from power-down condition Low power dissipation in idle mode INTEGRATION FEATURES ADSP-2100 family code compatible (easy to use algebraic syntax), with instruction set extensions Up to 256K byte of on-chip RAM, configured Up to 48K words program memory RAM Up to 56K words data memory RAM ...

Page 2

... Surface Mount Design .......................................... 46 Ordering Guide ..................................................... 47 REVISION HISTORY 8/06—Rev Rev. A Miscellaneous Format Updates.......................... Universal Applied Corrections or Additional Information to: Clock Signals ....................................................... 8 External Crystal Connections .................................. 8 ADSP-2185 Memory Architecture ............................ 9 Electrical Characteristics ....................................... 22 Absolute Maximum Ratings ................................... 23 ESD Diode Protection .......................................... 24 Memory Read ..................................................... 31 Memory Write .................................................... 32 Serial Ports ........................................................ 33 Outline Dimensions ............................................. 45 Ordering Guide ...

Page 3

... SRAM. This feature, combined with ADSP-21xx code compati- bility, provides a great deal of flexibility in the design decision. Specific family members are shown in Table Table 1. ADSP-218xN DSP Microcomputer Family Program Memory Device (K words) ADSP-2184N 4 ADSP-2185N 16 ADSP-2186N 8 ADSP-2187N 32 ADSP-2188N 48 ADSP-2189N 32 ADSP-218xN series members combine the ADSP-2100 family ...

Page 4

... ADSP-218xN series members incorporate two complete syn- chronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Following is a brief list of the capabilities of the ADSP-218xN SPORTs. For additional information on Serial Ports, refer to the ADSP-218x DSP Hardware Reference. • SPORTs are bidirectional and have a separate, double- buffered transmit and receive section. • ...

Page 5

... Considered as standard operating settings. Using these configurations allows for easier design and better memory management. Setting Memory Mode Memory Mode selection for the ADSP-218xN series is made during chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP’s PF2 pin, so care must be taken in how the mode selection is made ...

Page 6

... Power-down acknowledge pin (PWDACK) indicates when the processor has entered power-down. Idle When the ADSP-218xN is in the Idle Mode, the processor waits indefinitely in a low-power state until an interrupt occurs. When an unmasked interrupt occurs serviced; execution then continues with the instruction following the IDLE instruc- tion ...

Page 7

... Programmable wait state generation allows the processor to connect easily to slow peripheral devices. ADSP-218xN series members also provide four external inter- rupts and two serial ports or six external interrupts and one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to a single address bit (A0) ...

Page 8

... Figure 3. External Crystal Connections RESET The RESET signal initiates a master reset of the ADSP-218xN. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time ...

Page 9

... MEMORY ARCHITECTURE The ADSP-218xN series provides a variety of memory and peripheral interface options. The key functional groups are Pro- gram Memory, Data Memory, Byte Memory, and I/O. Refer to PROGRAM MEMORY MODEB = 1 0x3FFF RESERVED 0x2000 0x1FFF EXTERNAL PM 0x0000 PROGRAM MEMORY MODEB = 1 0x3FFF RESERVED ...

Page 10

... INTERNAL PM 0x0000 0x0000 Figure 9. ADSP-2189 Memory Architecture DSPs of this series have up to 48K words of Program Memory RAM on chip, and the capability of accessing up to two 8K external memory overlay spaces, using the external data bus. Rev Page August 2006 DATA MEMORY ...

Page 11

... Data Memory RAM on-chip. Part of this space is used by 32 memory-mapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus. Table 5. DMOVLAY Bits Processor DMOVLAY ADSP-2184N No Internal Overlay Region ADSP-2185N 0 ADSP-2186N No Internal Overlay Region ADSP-2187N ADSP-2188N ...

Page 12

... BDMA feature. The byte memory space consists of 256 pages, each of which is 16K The byte memory space on the ADSP-218xN series supports read and write operations as well as four different data formats. The byte memory uses data bits 15–8 for data. The byte mem- ory uses data bits 23– ...

Page 13

... Host uses IS and IRD (or IWR) to read (or write) DSP internal memory (PM or DM). 5. Host checks IACK line to see if the DSP has completed the previous IDMA operation. 6. Host ends IDMA transfer. Table 8. IDMA/BDMA Overlay Bits Processor ADSP-2184N ADSP-2185N ADSP-2186N ADSP-2187N ADSP-2188N ADSP-2189N Rev Page August 2006 ADSP-218xN 13. ...

Page 14

... A0. IDMA Port Booting ADSP-218xN series members can also boot programs through its internal DMA port. If Mode Mode and Mode the ADSP-218xN boots from the IDMA port. IDMA feature Table 8. Refer to the can load as much on-chip memory as desired. Program execu- tion is held off until the host writes to on-chip program memory location 0 ...

Page 15

... Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, • Asserting the bus grant (BG) signal, and • Halting program execution Mode is enabled, the ADSP-218xN will not halt program execution until it encounters an instruction that requires an external memory access ADSP-218xN series member is performing an external ...

Page 16

... These pins have no function except during emulation, and do not require pull-up or pull- down resistors. The traces for these signals between the ADSP-218xN and the connector must be kept as short as possi- ble, no longer than 3 inches. The following pins are also used by the EZ-ICE: BR, BG, RESET, and GND ...

Page 17

... EZ-ICE board’s DSP. ADDITIONAL INFORMATION This data sheet provides a general overview of ADSP-218xN series functionality. For additional information on the architec- ture and instruction set of the processor, refer to the ADSP-218x DSP Hardware Reference and the ADSP-218x DSP Instruction Set Reference. Rev Page August 2006 ...

Page 18

... ADSP-218xN PIN DESCRIPTIONS ADSP-218xN series members are available in a 100-lead LQFP package and a 144-ball BGA package. In order to maintain max- imum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are Table 9 ...

Page 19

... SPORT configuration determined by the DSP System Control Register. Software configurable. MEMORY INTERFACE PINS ADSP-218xN series members can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities ...

Page 20

... ADSP-218xN Table 12. Unused Pin Terminations (Continued) I/O 3-State 1 2 Pin Name (Z) D23–8 I/O ( I/O (Z) IWR I/O (Z) IRD I/O (Z) IAL I/O ( I/O (Z) IACK D2–0 or I/O (Z) IAD15–13 I/O (Z) PMS O (Z) DMS O (Z) BMS O (Z) IOMS O (Z) CMS (Z) BGH O IRQ2/PF7 I/O (Z) ...

Page 21

... High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1 prior to enabling interrupts, and let pins float. Reset 3 State Hi-Z Caused By Unused Configuration I Float O Float I Float I Float I Float O Float Rev Page August 2006 ADSP-218xN ...

Page 22

... AMB 1 Specifications subject to change without notice. 2 The ADSP-218xN is 3.3 V tolerant (always accepts up to 3.6 V max V approximately equals V (max). This 3.3 V tolerance applies to bidirectional pins (D23–D0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13–A1, PF7–PF0) and input- DDEXT only pins (CLKIN, RESET, BR, DR0, DR1, PWD). ...

Page 23

... Three-statable pins: A13–A1, D23–D0, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF7–PF0 BR. 9 Idle refers to ADSP-218xN state of operation during execution of IDLE instruction. Deasserted pins are driven to either measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 12, 13, 14), 30% are Type 2 and Type DD 6, and 20% are idle instructions ...

Page 24

... The bootstrap Schottky diode is connected between the core and I/O power supplies, as shown in Figure ADSP-218xN processor from partially powering the I/O supply. Including a Schottky diode will shorten the delay between the supply ramps and thus prevent damage to the ESD diode pro- tection circuitry ...

Page 25

... The output enable time (t a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in Figure the measurement value is that of the first pin to start driving. Rev Page August 2006 ADSP-218xN t MEASURED t V DIS OH V (MEASURED) – ...

Page 26

... CKH CK Output Drive Currents Figure 21 shows typical I-V characteristics for the output driv- ers on the ADSP-218xN series.The curves represent the current drive capability of the output drivers as a function of output voltage. Figure 23 shows the typical power-down supply current. Capacitive Loading ...

Page 27

... ARE AND AND 2 0% ARE IDLE INSTRUCTIO NS. 4 IDLE TATE OF OP ERATION DURI NG EX ECUTI DLE INSTRUCTION. DE ASSE RTE D PINS ARE DRI VEN TO EI THE GND. DD Figure 22. Power vs. Frequency NOTES 1. REFLECTS ADSP-218xN OPERATION IN LOWEST POWER CURRENT REFLECTS DEVICE OPERATING WITH 0mW 10 .5mW 10 5 4.3 mW Figure 24 ...

Page 28

... ADSP-218xN Clock Signals and Reset Table 15. Clock Signals and Reset Parameter Timing Requirements: t CLKIN Period CKI t CLKIN Width Low CKIL t CLKIN Width High CKIH Switching Characteristics: t CLKOUT Width Low CKL t CLKOUT Width High CKH t CLKIN High to CLKOUT High CKOH Control Signals Timing Requirements: ...

Page 29

... IFS IFH following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-218x DSP Hardware Reference for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced. ...

Page 30

... BGH High to xMS, RD, WR Enable SEH asynchronous signal meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships. 2 xMS = PMS, DMS, CMS, IOMS, BMS. 3 BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue ...

Page 31

... ASR CRD t RDD DATA LINES FOR ACCESSES ARE: BDMA: D15–8 I/O SPACE: D23–8 EXTERNAL DM: D23–8 EXTERNAL PM: D23–0 Figure 29. Memory Read Rev Page August 2006 ADSP-218xN Min Max 0.5t – 0.75t – 0.5t – 0.25t – 2 0.25t + ...

Page 32

... ADSP-218xN Memory Write Table 19. Memory Write Parameter Switching Characteristics: t Data Setup before WR High DW t Data Hold after WR High Pulse Width Low to Data Enabled WDE t A13–0, xMS Setup before WR Low ASW t Data Disable before Low DDR t CLKOUT High to WR Low CWR t A13– ...

Page 33

... RFS (Multichannel, Frame Delay Zero Valid RDV CLKOUT SCLK DR TFS IN RFS IN RFS O UT TFS TFS LTER FRA RFS LTIC ODE , MFD = 0 ) TFS IN ALTE RFS IN MU LTIC ODE , MFD = Figure 31. Serial Ports Rev Page August 2006 ADSP-218xN Min Max 0.25t 0.25t + Unit ...

Page 34

... ADSP-218xN IDMA Address Latch Table 21. IDMA Address Latch Parameter Timing Requirements: t Duration of Address Latch IALP t IAD15–0 Address Setup Before Address Latch End IASU t IAD15–0 Address Hold After Address Latch End IAH t IACK Low before Start of Address Latch IKA t Start of Write or Read After Address Latch End ...

Page 35

... If Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications t IACK IS IWR IAD15– IDSU IDH , t . IKSU IKH t IKW t IKHW t IWP t IDH t IDSU DATA Figure 33. IDMA Write, Short Write Cycle Rev Page August 2006 ADSP-218xN Min Max Unit ...

Page 36

... If Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications t 4 This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual. IACK IS IWR IAD15– ...

Page 37

... Second half of PM read. IACK IS IRD IAD15– IKHR t IKR t t IKDS IRDE PREVIOUS READ DATA DATA t IRDV t t IRDH1 OR IRDH2 Figure 35. IDMA Read, Long Read Cycle Rev Page August 2006 ADSP-218xN Min Max 0.5t – – – IRK t IKDH t IKDD Unit ...

Page 38

... ADSP-218xN IDMA Read, Short Read Cycle Table 25. IDMA Read, Short Read Cycle 1, 2 Parameter Timing Requirements: t IACK Low Before Start of Read IKR t Duration of Read (DM/PM1) IRP1 t Duration of Read (PM2) IRP2 Switching Characteristics: t IACK High After Start of Read IKHR t IAD15–0 Data Hold After End of Read ...

Page 39

... Disabled by default. 2 Start of Read = IS Low and IRD Low. Previous data remains until end of read. 3 End of Read = IS High or IRD High 15– IRD IES FIN ITE Figure 37. IDMA Read, Short Read Cycle in Short Read Only Mode Rev Page August 2006 ADSP-218xN Min Max Unit ...

Page 40

... Bit 10 (SPORT1 configure) of the System Control Register. If Bit these pins have serial port func- tionality. If Bit these pins are the external interrupt and flag pins. This bit is set default, upon reset. ADSP-218xN TOP VIEW (Not to Scale) Figure 38. 100-Lead LQFP Pin Configuration Rev ...

Page 41

... Rev Page August 2006 ADSP-218xN Pin Name EBR BR EBG BG D0/IAD13 D1/IAD14 D2/IAD15 D3/IACK V DDINT GND D4/IS D5/IAL D6/IRD D7/IWR D8 GND V DDEXT D9 D10 D11 GND D12 D13 D14 D15 D16 D17 D18 D19 GND D20 D21 D22 D23 FL2 FL1 FL0 ...

Page 42

... ADSP-218xN BGA PACKAGE PINOUT The BGA package pinout is shown in Figure 39 Pin names in bold text in the table replace the plain text named functions when Mode sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the ...

Page 43

... G09 G10 G11 G12 H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 J01 J02 Rev Page August 2006 ADSP-218xN Pin Name V DDEXT A8/IAD7 FL0 PF0 [MODE A] FL2 PF3 [MODE D] GND GND V DDEXT GND D10 A13/IAD12 NC A12/IAD11 A11/IAD10 ...

Page 44

... ADSP-218xN Table 28. BGA Package Pinout (Continued) Ball No. Pin Name J03 NC J04 V DDEXT J05 V DDEXT J06 SCLK0 J07 D0/IAD13 J08 RFS1/IRQ0 J09 BG J10 D1/IAD14 J11 V DDINT J12 V DDINT K01 NC K02 NC K03 NC K04 BMS K05 DMS K06 RFS0 K07 TFS1/IRQ1 K08 SCLK1 K09 ...

Page 45

... MIN 0.50 0.45 0.40 (BALL DIAMETER, SEE NOTE 4) Figure 40. 144-Ball BGA [CSP_BGA] (BC-144-6) 16.00 BSC SQ 14.00 BSC SQ 12° 100 1 TYP TOP VIEW (PINS DOWN) VIEW 0.27 0.50 BSC 0.22 0.17 Rev Page August 2006 ADSP-218xN A1 CORNER INDEX AREA 1.11 ...

Page 46

... ADSP-218xN SURFACE MOUNT DESIGN Table 29 is provided as an aid to PCB design. For industry-stan- dard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Table 29. BGA Data for Use with Surface Mount Design Ball Attach Solder Mask ...

Page 47

... ADSP-2185NBCA-320 –40°C to +85°C ADSP-2185NBST-320 –40°C to +85°C 2 ADSP-2185NBSTZ-320 –40°C to +85°C ADSP-2185NKCA-320 0°C to 70°C ADSP-2185NKST-320 0°C to 70°C 2 ADSP-2185NKSTZ-320 0°C to 70°C ADSP-2186NBCA-320 –40°C to +85°C ADSP-2186NBST-320 –40°C to +85°C 2 ADSP-2186NBSTZ-320 – ...

Page 48

... ADSP-218xN © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02666-0-8/06(A) Rev Page August 2006 ...

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