ADSP-2186 Analog Devices, ADSP-2186 Datasheet

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ADSP-2186

Manufacturer Part Number
ADSP-2186
Description
DSP Microcomputer
Manufacturer
Analog Devices
Datasheet

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a
ICE-Port is a trademark of Analog Devices, Inc.
All trademarks are the property of their respective holders.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
PERFORMANCE
25 ns Instruction Cycle Time 40 MIPS Sustained
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
40K Bytes of On-Chip RAM, Configured as
Dual Purpose Program Memory for Both Instruction
Independent ALU, Multiplier/Accumulator and Barrel
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP
144-Ball Mini-BGA
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
4 MByte Byte Memory Interface for Storage of Data
8-Bit DMA to Byte Memory for Transparent Program
I/O Memory Interface with 2048 Locations Supports
Programmable Memory Strobe and Separate I/O Memory
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Performance
Every Instruction Cycle
Power Dissipation with 100 Cycle Recovery from
Power-Down Condition
Set Extensions
8K Words On-Chip Program Memory RAM and
8K Words On-Chip Data Memory RAM
and Data Storage
Shifter Computational Units
Zero Overhead Looping Conditional Instruction
Execution
On-Chip Memory (Mode Selectable)
Tables and Program Overlays
and Data Memory Transfers (Mode Selectable)
Parallel Peripherals (Mode Selectable)
Space Permits “Glueless” System Design
Hardware and Automatic Data Buffering
(Mode Selectable)
GENERAL DESCRIPTION
The ADSP-2186 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2186 combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
The ADSP-2186 integrates 40K bytes of on-chip memory con-
figured as 8K words (24-bit) of program RAM and 8K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equip-
ment. The ADSP-2186 is available in 100-lead LQFP and
144-Ball Mini-BGA packages.
In addition, the ADSP-2186 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking for increased flexibility.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
DATA ADDRESS
GENERATORS
DAG 1
Automatic Booting of On-Chip Program Memory from
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging
ALU
ARITHMETIC UNITS
ADSP-2100 BASE
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Signaling
in Final Systems
ARCHITECTURE
DAG 2
MAC
SHIFTER
SEQUENCER
FUNCTIONAL BLOCK DIAGRAM
PROGRAM
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
PROGRAM MEMORY ADDRESS
World Wide Web Site: http://www.analog.com
DSP Microcomputer
PROGRAM
MEMORY
SPORT 0
8K
SERIAL PORTS
POWER-DOWN
24
MEMORY
CONTROL
SPORT 1
MEMORY
8K
DATA
16
ADSP-2186
© Analog Devices, Inc., 1999
PROGRAMMABLE
TIMER
FLAGS
AND
I/O
FULL MEMORY
CONTROLLER
EXTERNAL
EXTERNAL
EXTERNAL
INTERNAL
ADDRESS
HOST MODE
BYTE DMA
DATA
DATA
PORT
DMA
BUS
BUS
BUS
MODE
OR

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