ADSP-2187L Analog Devices, ADSP-2187L Datasheet

ADSP-2187L

Manufacturer Part Number

ADSP-2187L

Description

DSP Microcomputer

Manufacturer

Analog Devices

Datasheet

1.ADSP-2187L.pdf (32 pages)

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ICE-Port is a trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

FEATURES

PERFORMANCE

19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby

Low Power Dissipation in Idle Mode

INTEGRATION

ADSP-2100 Family Code Compatible, with Instruction

160K Bytes of On-Chip RAM, Configured as 32K Words

Dual Purpose Program Memory for Instruction and Data

Independent ALU, Multiplier/Accumulator and Barrel

Two Independent Data Address Generators

Powerful Program Sequencer Provides Zero Overhead

Programmable 16-Bit Interval Timer with Prescaler

100-Lead TQFP

SYSTEM INTERFACE

16-Bit Internal DMA Port for High Speed Access to

4 MByte Memory Interface for Storage of Data Tables

8-Bit DMA to Byte Memory for Transparent Program

I/O Memory Interface with 2048 Locations Supports

Programmable Memory Strobe and Separate I/O Memory

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding

Automatic Booting of On-Chip Program Memory from

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

UART Emulation through Software SPORT Reconfiguration

ICE-Port™ Emulator Interface Supports Debugging in

Sustained Performance

Every Instruction Cycle

Power Dissipation with 400 Cycle Recovery from

Power-Down Condition

Set Extensions

Program Memory RAM and 32K Words

Data Memory RAM

Storage

Shifter Computational Units

Looping Conditional Instruction Execution

On-Chip Memory (Mode Selectable)

and Program Overlays (Mode Selectable)

and Data Memory Transfers (Mode Selectable)

Parallel Peripherals (Mode Selectable)

Space Permits “Glueless” System Design

Hardware and Automatic Data Buffering

Byte-Wide External Memory, e.g., EPROM, or

Through Internal DMA Port

Signaling

Final Systems

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

GENERAL NOTE

This data sheet represents specifications for the ADSP-2187L

3.3 V processor.

GENERAL DESCRIPTION

The ADSP-2187L is a single-chip microcomputer optimized for

digital signal processing (DSP) and other high speed numeric

processing applications.

The ADSP-2187L combines the ADSP-2100 family base archi-

tecture (three computational units, data address generators and

a program sequencer) with two serial ports, a 16-bit internal

DMA port, a byte DMA port, a programmable timer, Flag I/O,

extensive interrupt capabilities and on-chip program and data

memory.

The ADSP-2187L integrates 160K bytes of on-chip memory

configured as 32K words (24-bit) of program RAM, and 32K

words (16-bit) of data RAM. Power-down circuitry is also pro-

vided to meet the low power needs of battery operated portable

equipment. The ADSP-2187L is available in 100-lead TQFP

package.

In addition, the ADSP-2187L supports new instructions, which

include bit manipulations—bit set, bit clear, bit toggle, bit test—

new ALU constants, new multiplication instruction (x squared),

biased rounding, result free ALU operations, I/O memory trans-

fers and global interrupt masking, for increased flexibility.

Fabricated in a high speed, low power, CMOS process, the

ADSP-2187L operates with a 19 ns instruction cycle time. Ev-

ery instruction can execute in a single processor cycle.

DATA ADDRESS

GENERATORS

DAG 1

ALU

ARITHMETIC UNITS

ADSP-2100 BASE

ARCHITECTURE

DAG 2

MAC

SEQUENCER

SHIFTER

PROGRAM

FUNCTIONAL BLOCK DIAGRAM

PROGRAM MEMORY DATA

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

DATA MEMORY DATA

(

32K 24 PM

8K 24 OVERLAY 1

8K 24 OVERLAY 2

World Wide Web Site: http://www.analog.com

DSP Microcomputer

SPORT 0

SERIAL PORTS

POWER-DOWN

CONTROL

MEMORY

) (

SPORT 1

32K 16 DM

8K 16 OVERLAY 1

8K 16 OVERLAY 2

ADSP-2187L

)

TIMER

PROGRAMMABLE

FLAGS

AND

I/O

FULL MEMORY

HOST MODE

CONTROLLER

EXTERNAL

INTERNAL

ADDRESS

BYTE DMA

PORT

DATA

DMA

BUS

MODE

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