ADSP-BF536-BBC-3A Analog Devices, ADSP-BF536-BBC-3A Datasheet

ADSP-BF536-BBC-3A

Manufacturer Part Number

ADSP-BF536-BBC-3A

Description

Manufacturer

Analog Devices

Datasheet

1.ADSP-BF536-BBC-3A.pdf (68 pages)

Specifications of ADSP-BF536-BBC-3A

Case

BGA

Date_code

0728+

Current page: 1 of 68
Download datasheet (3Mb)

FEATURES

Up to 600 MHz high performance Blackfin processor

0.8 V to 1.2 V core V

2.5 V and 3.3 V-tolerant I/O with specific 5 V-tolerant pins

182-ball and 208-ball MBGA packages

MEMORY

Up to 132K bytes of on-chip memory comprised of:

External memory controller with glueless support for SDRAM

Flexible booting options from external flash, SPI and TWI

Memory management unit providing memory protection

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

RISC-like register and instruction model for ease of

Advanced debug, trace, and performance monitoring

Instruction SRAM/cache; instruction SRAM;

and asynchronous 8-bit and 16-bit memories

memory or from SPI, TWI, and UART host devices

40-bit shifter

programming and compiler-friendly support

scratchpad SRAM (see

memory configurations)

data SRAM/cache; additional dedicated data SRAM;

with on-chip voltage regulation

EXTERNAL

ACCESS

Table 1 on Page 3

BUS

INSTRUCTION

VOLTAGE REGULATOR

MEMORY

FLASH, SDRAM CONTROL

EXTERNAL PORT

for available

Figure 1. Functional Block Diagram

MEMORY

DATA

DMA CORE BUS

ADSP-BF534/ADSP-BF536/ADSP-BF537

JTAG TEST AND EMULATION

BOOT ROM

CONTROLLER

INTERRUPT

DMA

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

PERIPHERALS

IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and

Controller area network (CAN) 2.0B interface

Parallel peripheral interface (PPI), supporting ITU-R 656

Two dual-channel, full-duplex synchronous serial ports

12 peripheral DMAs, 2 mastered by the Ethernet MAC

Two memory-to-memory DMAs with external request lines

Event handler with 32 interrupt inputs

Serial peripheral interface (SPI)-compatible

Two UARTs with IrDA

Two-wire interface (TWI) controller

Eight 32-bit timer/counters with PWM support

Real-time clock (RTC) and watchdog timer

32-bit core timer

48 general-purpose I/Os (GPIOs), 8 with high current drivers

On-chip PLL capable of 1 to 63 frequency multiplication

Debug/JTAG interface

PERIPHERAL ACCESS BUS

ADSP-BF537 only)

video data formats

(SPORTs), supporting eight stereo I

Embedded Processor

WATCHDOG TIMER

support

ETHERNET MAC

(ADSP-BF536/

BF537 ONLY)

TIMERS 0-7

UART 0-1

SPORT0

SPORT1

CAN

RTC

TWI

PPI

SPI

S channels

Blackfin

PORT

GPIO

PORT

GPIO

www.analog.com

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