ADUC848 Analog Devices, ADUC848 Datasheet
ADUC848
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ADUC848 Summary of contents
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... FEATURES High resolution Σ-∆ ADCs 2 independent 24-bit ADCs on the ADuC845 Single 24-bit ADC on the ADuC847 and single 16-bit ADC on the ADuC848 ADC input channels on all parts 24-bit no missing codes 22-bit rms (19.5 bit p-p) effective resolution Offset drift 10 nV/°C, gain drift 0.5 ppm/°C chop enabled ...
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... ADuC845/ADuC847/ADuC848 TABLE OF CONTENTS Specifications..................................................................................... 4 Abosolute Maximum Ratings ....................................................... 10 ESD Caution................................................................................ 10 Pin Configurations and Function Descriptions ......................... 11 General Description ....................................................................... 15 8052 Instruction Set ................................................................... 18 Timer Operation......................................................................... 18 ALE............................................................................................... 18 External Memory Access........................................................... 18 Complete SFR Map .................................................................... 19 Functional Description .................................................................. 20 8051 Instruction Set ................................................................... 20 Memory Organization ............................................................... 22 Special Function Registers (SFRs)............................................ 24 ADC Circuit Information.......................................................... 26 Auxiliary ADC (ADuC845 Only) ...
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... Changes to Figure 1...........................................................................1 Changes to the Burnout Current Sources Section ......................32 Changes to the Excitation Currents Section................................36 Changes to Table 30 ........................................................................47 Changes to the Flash/EE Memory on the ADuC845, ADuC847, ADuC848 Section......................................................................48 Changes to Figure 39 ......................................................................57 Changes to On-Chip PLL (PLLCON) Section ............................60 Added 3 V Part Section Heading ..................................................88 Added 5 V Part Section ..................................................................88 Changes to Figure 70 ...
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... ADC, unless otherwise noted. Core speed = 1.57 MHz (default CD = 3), unless otherwise noted. Table 1. Parameter PRIMARY ADC Conversion Rate 2 No Missing Codes Resolution (ADuC845/ADuC847) Resolution (ADuC848) Output Noise (ADuC845/ADuC847) Output Noise (ADuC848) Integral Nonlinearity 3 Offset Error 2 Offset Error Drift vs. Temperature 4 Full-Scale Error ADuC845/ADuC847 ADuC848 4 Gain Error Drift vs ...
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... Rev Page 5 of 108 ADuC845/ADuC847/ADuC848 Conditions 50 Hz/60 Hz ± 1 Hz, 16.6 Hz Fadc 52H, chop on, REJ60 ± 1 Hz, 16.6 Hz Fadc 52H, chop on 50 Hz/60 Hz ± Fadc 52H, chop off, REJ60 ± Fadc 52H, chop off T = 85° ...
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... ADuC845/ADuC847/ADuC848 Parameter AUXILIARY ADC ANALOG INPUTS (ADuC845 Only Differential Input Voltage Ranges Bipolar Mode (ADC1CON Unipolar Mode (ADC1CON Average Analog Input Current Analog Input Current Drift Absolute AIN/AINCOM Voltage 2, 7 Limits 2 Normal Mode Rejection 50 Hz/ AIN and REFIN ADC SYSTEM CALIBRATION ...
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... Rev Page 7 of 108 ADuC845/ADuC847/ADuC848 Conditions AIN+ is the selected positive input (AIN4 or AIN6 only) to the primary ADC AIN− is the selected negative input (AIN5 or AIN7 only) to the primary ADC Available from each current source Matching between both current sources ± ...
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... ADuC845/ADuC847/ADuC848 Parameter LOGIC OUTPUTS (All Digital Outputs except XTAL2 Output High Voltage Output Low Voltage OL 2 Floating State Leakage Current Floating State Output Capacitance START-UP TIME At Power-On After Ext RESET in Normal Mode After WDT RESET in Normal Mode From Power-Down Mode ...
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... Current DD 1 Temperature range is for ADuC845BS; for the ADuC847BS and ADuC848BS (MQFP package), the range is –40°C to +125°C. Temperature range for ADuC845BCP, ADuC847BCP, and ADuC848BCP (LFCSP package) is –40°C to +85°C. 2 These numbers are not production tested but are guaranteed by design and/or characterization data on production release. ...
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... Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ________________________ 1 AGND and DGND are shorted internally on the ADuC845, ADuC847, and ADuC848. 2 Applies to the P1.0 to P1.7 pins operating in analog or digital input modes. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection ...
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... Reference Input, Negative Terminal. I External Differential Reference Input, Positive Terminal. Rev Page 11 of 108 ADuC845/ADuC847/ADuC848 1 P2.7/PWMCLK P2.6/PWM1 PIN 1 IDENTIFIER 3 40 P2.5/PWM0 4 39 P2.4/T2EX 5 DGND 38 ADuC845/ADuC847/ADuC848 6 37 DGND XTAL2 TOP VIEW (Not to Scale XTAL1 10 33 P2.3/SS/T2 11 P2.2/MISO ...
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... ADuC845/ADuC847/ADuC848 Pin No: Pin No: 56- 52-MQFP LFCSP Mnemonic 9 9 P1.4/AIN5 10 10 P1.5/AIN6 11 11 P1.6/AIN7/IEXC1 12 12 P1.7/AIN8/IEXC2 13 13 AINCOM/DAC 14 14 DAC ---- 15 AIN9 ---- 16 AIN10 15 17 RESET 16– 19 18– 21 P3.0–P3 .7 22–25 24– P3.0/RxD 17 19 P3.1/TxD 18 20 P3.2/INT0 19 21 P3.3/INT1 22 24 P3.4/ P3.5/ ...
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... F7FFH. No external program memory acce ADuC847, or ADuC848. To determine the mode of code execution, the EA pin is sampled at the end of an external RESET assertion or as part of a device power cycle. EA can also be used as an external emulation I/O pin, and ...
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... ADuC845/ADuC847/ADuC848 Pin No: Pin No: 56- 52-MQFP LFCSP Mnemonic 43–46, 46–49, 52– P0.0–P0.7 49– input output supply. 1 Type Description I/O These pins are part of Port 0, which is an 8-bit open-d port. Port 0 pins that have 1s written to them float, and, in that state, can be used as high impedance inputs. An external pull-up resistor is required on P0 outputs to force a valid logic high level externally ...
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... The ADuC845 includes two (primary and auxiliary) 24-bit Σ-Δ ADCs with internal buffering and PGA on the primary ADC. The ADuC847 includes the same primary ADC as the ADuC845 (auxiliary ADC removed). The ADuC848 is a 16-bit ADC version of the ADuC847. The ADCs incorporate flexible input multiplexing, a temperature sensor (ADuC845 only), and a PGA (primary ADC only) allowing direct measurement of low-level signals ...
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... ADuC845/ADuC847/ADuC848 AIN1 56 AIN2 1 AIN3 2 AIN4 3 BUF AIN5 9 AIN AIN6 10 MUX AIN7 11 AUXILIARY ADC AIN8 12 AIN9 15 AIN10 16 AINCOM/DAC 13 BAND GAP REFERENCE TEMP SENSOR REFIN+ 8 REFIN– 7 200µA 200µA CURRENT IEXC1 11 SOURCE IEXC2 12 MIX ...
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... CORE 11-BIT STACK POINTER DOWNLOADER DEBUGGER UART UART SERIAL PORT TIMER Figure 5. Detailed Block Diagram of the ADuC847 Rev Page 17 of 108 ADuC845/ADuC847/ADuC848 12-BIT DAC VOLTAGE BUF 14 CONTROL OUTPUT DAC DUAL 16-BIT 40 Σ-∆ DAC PWM ...
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... ALE On the ADuC834, the output on the ALE pin is a clock at 1/6th of the core operating frequency. On the ADuC845, ADuC847, and ADuC848, the ALE pin operates as follows. For a single machine cycle instruction, ALE is high for the entire machine cycle. For a two or more m for the first machine cycle and then low for the remainder of the machine cycles ...
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... TCON IT0 IE0 RESET DEFAUL 89H 0 88H 0 88H 00H SFR ADDRESS BIT ADDRESSABLE. Figure 7. Complete SFR Map for th e ADuC845, ADuC847, and ADuC848 Rev Page 19 of 108 ADuC845/ADuC847/ADuC848 DACL DACH DACCON RESERVED FBH 00H FCH 00H FDH 00H I2CADD1 NOT USED ...
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... ADuC845/ADuC847/ADuC848 FUNCTIO NAL DESCRIPTION 8051 INSTRUCTION SET Table 4 . Optimized Single-Cycle 8051 Instruc Mnemonic Arithmetic A A,Rn ADD A,@Ri ADD A,dir ADD A,#data ADDC A,Rn ADDC A,@Ri ADDC A,dir ADD A,#data SUBB A,Rn SUBB A,@Ri SUBB A,dir SUBB A,#data INC A INC Rn INC @Ri INC dir INC DPTR DEC A DEC Rn DEC @Ri ...
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... OR direct bit and carry OR direct bit inverse to carry Move direct bit to carry Move carry to direct bit Jump indirect relative to DPTR Return from subroutine Return from interrupt Absolute jump to subroutine Absolute jump unconditional Rev Page 21 of 108 ADuC845/ADuC847/ADuC848 Bytes Cycles ...
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... MOVX instructions are four cycles when they have 0 wait state. Cycles of MOVX instructio 3 LCALL instructions are three cycles when the LCALL instruction comes from an interrupt. MEMORY ORGANIZATION The ADuC845, ADuC847, and ADuC848 contain four memory blocks: • 62 kbytes/3 2 kbytes/8 kbytes of on-chip Flas memory • ...
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... Figure 8. Lower 128 Bytes of Internal Data Memory Internal XRAM The ADuC845, ADuC847, and ADuC848 contain 2 kbytes of on-chip extended data memory. This memory, although on- chip, is accessed via the MOVX instruction. The 2 kbytes of internal XRAM are mapped into the bottom 2 kbytes of the external address space if the CFG84x.0 (Table 7) bit is set ...
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... ADuC845/ADuC847/ADuC848 SPECIAL FUNCTION REGIST ERS (SFRs) The SFR space is mapped into the upper 128 bytes of internal data memory space and accessed by direct addre provides an inte face betwee r n the CPU and all on-chip periph- erals. A block diagra show m ing the programming model of the ...
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... Power-Down Mode Enable part enters power-down mode. 0 ----- Not Implemented. Write Don’t Care. ADuC845/ADuC847/ADuC848 Configuration Register (CFG845/CFG847/CFG848) The CFG845/CFG847/CFG848 SFR contains the bits necessary to configure the internal XRAM and the extended SP. By default, it configures the user into 8051 mode, that is, extended SP, and the internal XRAM are disabled ...
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... ADC CIRCUIT INFORMATION The ADuC845 incorporates two 10-channel (8-channel on th MQFP package) 24-bit Σ-∆ ADCs, while the ADuC847 and ADuC848 each incorporate a single 10-channel (8-channel on the MQFP package) 24-bit and 16-bit Σ-∆ ADC. Each part also includes an on-chip programmable gain amplifier and configurable buffering (neither is ava auxiliary ADC on the ADuC845) ...
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... Figure 12. Block Diagram of the ADC Inpu t Channel with Chop Enabled Rev Page 27 of 108 ADuC845/ADuC847/ADuC848 chop enabled, the ADC repeatedly reverses its inputs. The a positive offset and a negative offset term included from the filter is summed and averaged with the previous ...
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... ADuC845/ADuC847/ADuC848 Thi s offset i s remove d by performing a r Thi s average eans that the settling pro grammin ADC is twice the no whi le an asy nchron ous step change on th fully reflecte d until t he third subsequent × SETTLE ADC f ADC ...
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... Table 12. ADuC848 Typical Output Noise (µV) vs. Input Range and Update Rate with Chop Enabled SF Word Data Update Rate (Hz) 13 105.03 23 59.36 27 50.56 69 19.79 255 5.35 Table 13. ADuC848 Typical Peak-to-Peak Resolution (Bits) vs. Input Range and Update Rate with Chop Enabled SF Word Data Update Rate (Hz) 13 105.03 23 59.36 27 50.56 69 19.79 255 5.35 used in the implementation of the modulator ...
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... ADuC845/ADuC847/ADuC848 Signal Chain Overview with Chop Disabled (CHOP = 1) With CHOP = 1, chop is disabled and the available output rates vary from 16. 1.365 kHz. The range of applicable SF words is from 3 to 255. When switching between channels with chop disabled, the channel throughput rate is higher than wh chop is enabled ...
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... Typical Output R Data Up date ± Word Rate ( Hz) 3 1365.33 30.64 13 315.08 2.07 69 59.36 0.85 82 49.95 0.83 255 16.06 0.52 Table 17. ADuC848 Typical Peak-to-Peak Resolution (Bits Data Update SF Word Rate (Hz) ± 1365.33 7.5 13 315.08 11.5 68 59. 49.95 13 255 16.06 13.5 ed (CHOP = 1) source is quantization noise, which is added when the analog s input is converted to the digital domain ...
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... BURNOUT CURRENT SOURCES The primary ADC on the ADuC845 and the ADC on the ADuC847 and ADuC848 incorporate two 200 µA constant current genera connected sensor. One sources current from the AV AIN(+), and one sinks current from AIN(−) to AGND. These currents are only configurable for use on AIN5/AIN6 and/or AIN7/AIN8 in differential mode only, from the ICON ...
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... SF register is used. Σ-∆ MODULATOR A Σ-∆ ADC usually consists of two main blocks, an ana modulator, and a digital filter. For the ADuC845/ADuC847/ ADuC848, the analog modulator consists of a difference amplifier, an integrator block, a comparator, and a feedback DAC as shown in Figure 16. ANALOG ...
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... SF word that yields an ADC throughput that i less than 20 Hz with chop enabled (SF ≥ 68 decimal). ADC CHOPPING The ADCs on the ADuC845/ADuC847/ADuC848 implement a chopping scheme whereby the ADC repeatedly reverses its inputs. The decim ated digital output words from the Sinc ...
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... ADC does not incorporate a PGA, and the gain is fixed 2. unipolar mode, and ±2.50 V bipolar mode. BIPOLAR/UNIPOLAR CONFIGURATION The analog inputs of the ADuC845/ADuC847/ADuC848 can accept either unipolar or bipolar input voltage ranges. Bipolar a ed. input ranges do not imply that the part can handle negative voltages with respect to system AGND, but rather with respec to the negative reference input ...
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... V where: AIN is the analog input voltage. GAIN is the PGA gain setting, that is the 2.56 V range and 128 on the 20 mV range, and (16 on the ADuC848). The output code for any analog input voltage on the auxiliary ADC can be represented as follows: N Code = (AIN × ...
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... Rev Page 37 of 108 ADuC845/ADuC847/ADuC848 110 130 150 170 190 210 SF (Decimal) Figure 21 Normal Mode Rejection vs. SF, Chop On FREQUENCY (Hz) Figure 22. Chop Off, Fadc = 50 Hz 52H FREQUENCY (Hz) Figure 23 ...
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... ADuC845/ADuC847/ADuC848 0 –20 –40 –60 –80 –100 –120 FREQUENCY (Hz) Figure 24. Chop On, Fadc = 16.6 Hz 52H 0 –20 –40 –60 –80 –100 –120 Figure 25. Chop On, Fadc = 16.6 Hz 52H, REJ60 En Rev Page 38 of 108 FREQUENCY (Hz) abled ...
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... Register. Allows user control of the various on-chip current source options. ADC0L/M/H Primary ADC 24-b it (16-bit on the ADuC848) conversion result is held in these three 8-bit registers. ADC0L is not avai the ADuC848. ADC1L/M/H Auxiliary ADC 24-bit conversion result is held in these two 8-bit registers. ADuC845 only. ...
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... ADuC845/ADuC847/ADuC848 ADCSTAT (ADC STATUS REGI STER) This SFR reflects the status of both ADCs including data ready clu ding REFIN± reference detect and conversion overflow/un SFR Address: D8H Pow er-On Default: 00H Bit A ddressable: Yes Tabl e 23. ADCSTAT SFR Bit Designation Bit N o ...
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... ADC1H/M/L (ADuC845 only)) are updated. The relevant flags in the ADCSTAT SFR are written, and power-down is re-entered with the MD2−MD0 accordingly being written to 000. Note that ADC0L is not available on the ADuC848 Continuous Conversion. In continuous conversion mode, the ADC data registers are regularly updated at the selected update rate (see the Sinc Filter SFR Bit Designations in Table 28) ...
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... ADuC845/ADuC847/ADuC848 Notes on the ADCMODE Register • Any change to the MD bits immediately resets both ADCs (auxiliary ADC o nly applicab le to the ADuC845). A write to the MD2–MD bits w 0 ith no change in contents is also treated set. (See t he exception to this in the third note of this section.) • ...
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... V–320 mV in unip 0 1 ±640 V–640 mV in unip 1 0 ±1. V–1 . unipolar 1 1 ±2. V–2 unipolar mode) Rev Page 43 of 108 ADuC845/ADuC847/ADuC848 nge (V = 2.5 V) REF lar mode) ar mode) lar mode) olar mode) olar mode) olar mode) mode) ...
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... ADuC845/ADuC847/ADuC848 ADC0CON2 (PRIMARY ADC CHANNEL SELE ADC0CON2 is used to select a reference source and channel for the primary ADC. SFR Address: E6H Power-On Default: 00H Bit Addressable: No Table 26. ADC0CON2 SFR Bit Designations Bit N o. Name Descr 7, 6 XREF1, XREF0 Primary ADC Exte Set by the user to enable the primary ADC to use the external reference via REFIN± or REFIN2±. ...
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... Chop mode must be enabled for correct temperature sensor operation. The temperature sensor is factory calibrated to yield conversion results 800000H at 0°C (ADC chop on). A +1°C change in temperature results LSB change in the ADC1H register ADC conversion result. The temperature sensor is not available on the ADuC847 or ADuC848. NLY) Description Not Implemented. Write Don’ ...
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... ADuC845/ADuC847/ADuC848 SF (ADC SINC FILTER CONTROL REGISTER) The SF register is used to configure the decimation factor fo SFR Address: D4H Power-On Default: 45H Bit Addressable: No Table 28. Sinc Filter SFR Bit Designations SF.7 SF.6 SF The bits in this register set the decimation factor of the ADC. This has a d chop setting. The equations used to determine the ADC throughput rate a ...
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... ADC . Ther fore current source is changed while ourth output ast ( dep endi ng pin t her y inc eb rea Rev Page 47 of 108 ADuC845/ADuC847/ADuC848 n ADC statu s of the chop mode) to see a fully sing th e cur rent source capability to 400 µA. ...
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... Flash/EE memory. As indicated in the Specificatio ADuC848 Flash/EE memory endurance qualification has been carried out in accordance with JEDEC Specification A117 the industrial temperature range of –40°C, +25°C, +85°C, +125°C. (The LFCSP package is qualified to +85°C only.) The ...
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... This allows the user to download code to the full 62 kbytes of Flash/EE program memory while the device is in circuit in its target application hardware serial download executable (WSD.EXE) is provided as part of the ADuC845/ADuC847/ADuC848 Quick Start 90 100 110 development system. Application Note uC004 fully describes the serial download protocol that is used by the embedded download kernel ...
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... Figure 30. ULOAD mode can be used to upgrade the code in the field via any user-defined down load protocol. By configuring the SPI port on the ADuC845/ADuC847/ADuC848 as a sla is possible to completely reprogram the 56 kbytes of Flash/EE program memory in under 5 s (see Application Note uC007 “User Download Mode” at www.analog.com/microconverter). ...
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... The 4 kbytes of Flash/EE data memory are configured as 1024 pages, each of 4 bytes. As with the other ADuC845/ADuC847/ ADuC848 peripherals, the interface to this memory space is via a group of registers mapped in the SFR space. A group of four data registers (EDATA1–4) holds the 4 bytes of data at each page ...
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... ADuC845/ADuC847/ADuC848 Example: Programming the Flash/EE Data Memory A user wants to program F3H into the second byte on Page 03H of the Flash/EE data memory space while preserving the other 3 bytes already in this page. A typical program of the Flash/EE data array involves 1. Setting EADRH/L with the page address. ...
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... DAC CIRCUIT INFORMATION The ADuC845/ADuC847/ADuC848 incorporate a 12-bit, voltage output DAC on-chip. It has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF, and has two selectable ranges and can operate in 12-bit or REF DD 8-bit mode. The DAC has a control register, DACCON, and two data registers, DACH/L ...
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... ADuC845/ADuC847/ADuC848 Using the DAC The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is shown in Figure 33 REF R OUTPUT BUFFER R R HIGH-Z DISABLE (FROM MCU Figure 33. Resistor String DAC Functional Equivalent Features of this architecture include inherent guaranteed monotonicity and excellent differential linearity ...
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... DAC output remains at ground potential whenever the DAC is disabled. PULSE-WIDTH MODULATOR (PWM) The ADuC845/ADuC847/ADuC848 has a highly flexible PWM offering programmable resolution and an input clock. The PWM can be configured in six different modes of operation. Two of these modes allow the PWM to be configured as a Σ-∆ ...
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... ADuC845/ADuC847/ADuC848 PWMCON PWM Control SFR SFR Address: AEH Power-On Default: 00H Bit Addressable: No Table 34. PWMCON PWM Control SFR Bit No. Name Description 7 ––– Not Implemented. Write Don’t Care PWM2, PWM1, PWM0 PMW Mode Selection. PWM2 ...
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... PWM counter equals PWM0L. The output of PWM1 (P2.6) goes high when the PWM counter equals PWM1H and goes low again when the PWM counter equals PWM0H. Setting PWM1H to 0 ensures that both PWM outputs start simultaneously. PWM1H/L PWM0H/L 0 P2.5 Rev Page 57 of 108 ADuC845/ADuC847/ADuC848 PWM1H.1 PWM1H R/W R/W PWM1L.1 PWM1L.0 ...
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... ADuC845/ADuC847/ADuC848 Mode 3 (Twin 16-Bit PWM) In Mode 3, the PWM counter is fixed to count from 0 to 65536, giving a fixed 16-bit PWM. Operating from the 12.58 MHz core clock results in a PWM output rate of 192 Hz. The duty cycle of the PWM outputs at P2.5 and P2.6 are independently programmable. As shown in Figure 41, while the PWM counter is less than PWM0H/L, the output of PWM0 (P2 ...
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... PWM1H PWM0L 16-BIT PWM0H 0 16-BIT P2.5 P2.6 3.146MHz 16-BIT 0, 3/4, 1/2, 1/4, 0 16-BIT PWM1H/L = 4000H Mode 7 In Mode 7, the PWM is disabled, allowing P2.5 and P2 used as normal. Rev Page 59 of 108 ADuC845/ADuC847/ADuC848 CARRY OUT AT P2 318µs 16-BIT LATCH 16-BIT CARRY OUT AT P2.6 318µ ...
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... ADuC845/ADuC847/ADuC848 ON-CHIP PLL (PLLCON) The ADuC845/ADuC847/ADuC848 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple (384) of this to provide a stable 12.582912 MHz clock for the system. The core can operate at this frequency or at binary submultiples allow power saving when maximum core performance is not required ...
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... I C SERIAL INTERFACE The ADuC845/ADuC847/ADuC848 support a fully licensed serial interface. The I C interface is implemented as a full hardware slave and software master. SDATA (Pin 27 on the MQFP package and Pin 29 on the LFCSP package) is the data I/O pin. SCLK (Pin 26 on the MQFP package and Pin 28 on the LFCSP package) is the serial interface clock for the SPI interface ...
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... C peripheral addresses for the part. It may be overwritten by user code. Application http://www.analog.com/microconverter Software Master Mode 2 C interface are The ADuC845/ADuC847/ADuC848 can be used master device by configuring the I and writing software to output the data bit-by-bit. This is referred software master. Master mode is enabled by setting the I2CM bit in the I2CCON register. ...
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... Hardware Slave Mode After reset, the ADuC845/ADuC847/ADuC848 default to 2 hardware slave mode. The I C interface is enabled by clearing the SPE bit in SPICON. Slave mode is enabled by clearing the I2CM bit in I2CCON. The parts have a full hardware slave slave mode, the I C address is stored in the I2CADD register. ...
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... SS (Slave Select Input Pin) Pin 31 (MQFP Package), Pin 33 (LFCSP Package) The SS pin is used only when the ADuC845/ADuC847/ ADuC848 are configured in SPI slave mode. This line is active low. Data is received or transmitted in slave mode only when the SS pin is low, allowing the parts to be used in single-master, multislave SPI configurations ...
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... SPIDAT: SPI Data Register SFR Address: 7FH Power-On Default: 00H Bit Addressable: No SPR0 Selected Bit Rate core core core 1 f /16 core Rev Page 65 of 108 ADuC845/ADuC847/ADuC848 2 C simultaneously necessary to ...
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... Depending on the configuration of the bits in the SPICON SFR shown in Table 41, the SPI interface transmits or receives data in a number of possible modes. Figure 46 shows all possible ADuC845/ADuC847/ADuC848 SPI configurations and the timing relationships and synchronization among the signals involved. Also shown in this figure is the SPI interrupt bit (ISPI) and how it is triggered at the end of each byte-wide communication ...
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... DPTR is post-decremented after a MOVX or MOVC instruction. 1 DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction is useful for moving 8-bit blocks to/from 16-bit devices.) MOVELOOP: CLR A Rev Page 67 of 108 ADuC845/ADuC847/ADuC848 A7H 00H No MOV DPTR,#0 ;Main DPTR = 0 MOV DPCON,#55H ;Select shadow DPTR ...
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... ADuC845/ADuC847/ADuC848 POWER SUPPLY MONITOR The power supply monitor, once enabled, monitors the DV and AV supplies on the parts. It indicates when any of the DD supply pins drop below one of four user-selectable voltage trip points from 2. 4.63 V. For correct operation of the power supply monitor function, AV must be equal to or greater than DD 2 ...
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... WATCHDOG TIMER The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADuC845/ADuC847/ ADuC848 enters an erroneous state, possibly due to a program- ming error or electrical noise. The watchdog function can be disabled by clearing the WDE (watchdog enable) bit in the watchdog control (WDCON) SFR. When enabled, the ...
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... ADuC845/ADuC847/ADuC848 TIME INTERVAL COUNTER (TIC) A TIC is provided on-chip for counting longer intervals than the standard 8051-compatible timers can count. The TIC is capable of timeout intervals ranging from 1/128 second to 255 hours. Also, this counter is clocked by the external 32.768 kHz crystal rather than by the core clock, and it can remain active in power-down mode and time long power-down intervals ...
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... Cleared by the user to disable the clock to the time interval counters and reset the time interval SFRs to the last value written to them by the user. The time registers (HTHSEC, SEC, MIN, and HOUR) can be written while TCEN is low. Interval Timebase 1/128 Second Seconds Minutes Hours Rev Page 71 of 108 ADuC845/ADuC847/ADuC848 ...
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... ADuC845/ADuC847/ADuC848 INTVAL—User Timer Interval Select Register Function: User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt, if enabled. SFR Address: ...
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... SFR bit definitions. Parallel I/O The ADuC845/ADuC847/ADuC848 use four input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some are capable of external memory operations, while others are multiplexed with alternate functions for the peripheral functions available on-chip ...
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... ADuC845/ADuC847/ADuC848 P2.5 and P2.6 can also be used as PWM outputs, while P2.7 can act as an alternate PWM clock source. When selected as the PWM outputs, they overwrite anything written to P2.5 or P2.6. Table 47. Port 2 Alternate Functions Pin No. Alternate Function P2.0 SCLOCK for SPI P2.1 MOSI for SPI P2.2 MISO for SPI P2 ...
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... TIMERS/COUNTERS The ADuC845/ADuC847/ADuC848 have three 16-bit timer/ counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware is included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists of two 8-bit registers: THx and TLx ( 2). All three can be configured to operate either as timers or as event counters ...
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... ADuC845/ADuC847/ADuC848 TCON—Timer/Counter 0 and 1 Control Register SFR Address: 88H Power-On Default: 00H Bit Addressable: Yes Table 51. TCON SFR Bit Designations Bit No. Name Description 7 TF1 Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the program counter (PC) vectors to the interrupt service routine. ...
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... Timer 1 itself. CORE CLK INTERRUPT P3.4/T0 TH0 TF0 (8 BITS) P3.2/INT CLK/12 NOTES 1. THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE THE ON-CHIP PLL SECTION) Rev Page 77 of 108 ADuC845/ADuC847/ADuC848 1 C TL0 (8 BITS) C CONTROL TR0 RELOAD TH0 (8 BITS) 0 Figure 54. Timer/Counter 0, Mode 2 CORE ...
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... ADuC845/ADuC847/ADuC848 T2CON—Timer/Counter 2 Control Register SFR Address: C8H Power-On Default: 00H Bit Addressable: Yes Table 52. T2CON SFR Bit Designations Bit No. Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 cannot be set when either RCLK = 1 or TCLK = 1. Cleared by user software. ...
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... RELOAD RCAP2L RCAP2H CONTROL EXEN2 Figure 56. Timer/Counter 2, 16-Bit Autoreload Mode TL2 TH2 (8 BITS) (8 BITS CONTROL TR2 CAPTURE RCAP2L RCAP2H CONTROL EXEN2 Figure 57. Timer/Counter 2, 16-Bit Capture Mode Rev Page 79 of 108 ADuC845/ADuC847/ADuC848 TF2 TIMER INTERRUPT EXF2 TF2 TIMER INTERRUPT EXF2 ...
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... ADuC845/ADuC847/ADuC848 UART SERIAL INTERFACE The serial port is full duplex, meaning that it can transmit and receive simultaneously also receive buffered, meaning that it can begin receiving a second byte before a previously received byte is read from the receive register. However, if the first byte is still not read by the time reception of the second byte is complete, the first byte is lost ...
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... If any of these conditions is not met, the received frame is irretrievably lost, and RI is not set. Rev Page 81 of 108 ADuC845/ADuC847/ADuC848 Either SM2 = 0 or SM2 = 1 Received stop bit = 1 The 8 bits in the receive shift register are latched into SBUF. The 9th data bit is latched into RB8 in SCON. ...
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... ADuC845/ADuC847/ADuC848 Mode 3 (9-Bit UART with Variable Baud Rate) Mode 3 is selected by setting both SM0 and SM1. In this mode, the 8051 UART serial port operates in 9-bit mode with a variable baud rate determined by either Timer 1 or Timer 2. The opera- tion of the 9-bit UART is the same as for Mode 2, but the baud rate can be varied as for Mode 1 ...
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... Also, generating baud rates requires the exclusive use of a timer, rendering it unusable for other applications when the UART is required. To address this problem, the ADuC845/ADuC847/ADuC848 have a dedicated baud rate timer (Timer 3) specifically for generating highly accurate baud rates. Timer 3 can be used instead of Timer 1 or Timer 2 for generating very accurate high speed UART baud rates including 115200 and 230400 ...
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... ADuC845/ADuC847/ADuC848 T3FD—Timer 3 Fractional Divider Register See Table 57 for values. SFR Address: 9DH Power-On Default: 00H Bit Addressable: No Table 56. T3FD SFR Bit Designations Bit No. Name Description 7 ---- Not Implemented. Write Don’t Care. 6 ---- Not Implemented. Write Don’t Care. 5 T3FD.5 Timer 3 Fractional Divider Bit 5. ...
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... INTERRUPT SYSTEM The ADuC845/ADuC847/ADuC848 provide nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs: Interrupt Enable Register IE IP Interrupt Priority Register IEIP2 Secondary Interrupt Enable Register IE—Interrupt Enable Register SFR Address: ...
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... ADuC845/ADuC847/ADuC848 IEIP2—Secondary Interrupt Enable Register SFR Address: A9H Power-On Default: A0H Bit Addressable: No Table 60. IEIP2 Bit Designations Bit No. Name Description 7 ---- Not Implemented. Write Don’t Care. 6 PTI Time Interval Counter Interrupt Priority Setting (1 = High Low). 5 PPSM Power Supply Monitor Interrupt Priority Setting (1 = High Low). ...
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... HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC845/ADuC847/ADuC848 into any hardware system. EXTERNAL MEMORY INTERFACE In addition to their internal program and data memories, the parts can access Mbytes of external data memory (SRAM) ...
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... I/O pins, and those sourced grounds. DD the DAC to determine the total current needed at the ADuC845/ ADuC847/ADuC848 DV drawn from the DV during Flash/EE erase and program cycles. POWER-SAVING MODES Setting the power-down mode bit, PCON.1, in the PCON SFR described in Table 6, allows the chip to be switched from normal mode into full power-down mode ...
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... RECOMMENDATIONS As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADuC845/ ADuC847/ADuC848-based designs in order to achieve optimum performance from the ADCs and DAC. Although the parts have separate pins for analog and digital ground (AGND and DGND), the user must not tie these to ...
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... MicroConverter and therefore execute slightly different code if required. The CHIPID SFR reads as follows for the Σ-∆ ADC family of MicroConverter products. Note that the ADuC845/ADuC847/ADuC848 are treated as one part as far as the CHIPID is concerned. Table 63. CHIPID Values for Σ-∆ MicroConverter Products ...
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... From a hardware perspective, entry to serial port debug mode is identical to the serial download entry sequence described previously. In fact, both serial download and serial port debug modes are essentially one mode of operation used in two different ways. Rev Page 91 of 108 ADuC845/ADuC847/ADuC848 DV DD 1kΩ 2-PIN HEADER FOR EMULATION ACCESS ...
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... V voltage reference. The preceding example shows just a single differential ADC connection using a single reference input pair. The ADuC845/ ADuC847/ADuC848 have the capability of connecting to five differential inputs directly or ten single-ended inputs (LFCSP package only) as well as having a second reference input. This ...
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... R 15 AIN9 AIN10 16 P1.3/AIN4/REFIN2– RESET ACTIVE HIGH. (NORMALLY OPEN RS232 CONNECTION Figure 71. Dual Reference Typical Connectivity Rev Page 93 of 108 ADuC845/ADuC847/ADuC848 DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) 1kΩ 1kΩ DGND LFCSP PACKAGE DV DD XTAL2 35 XTAL1 34 19 ...
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... ADuC845/ADuC847/ADuC848 QuickStart DEVELOPMENT SYSTEM The QuickStart Development System is an entry-level, low cost development tool suite supporting the ADuC8xx MicroConverter product family. The system consists of the following PC-based (Windows®-compatible) hardware and software development tools: Hardware: Evaluation board and serial port programming cable ...
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... Machine Cycle Time CYC 1 ADuC845/ADuC847/ADuC848 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 12.58 MHz internal clock for the system. The core can operate at this frequency binary submultiple called Core_Clk, selected via the PLLCON SFR. 2 This number is measured at the default Core_Clk operating frequency of 1 ...
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... ADuC845/ADuC847/ADuC848 Table 65. EXTERNAL DATA MEMORY READ CYCLE Parameter t RD Pulse Width RLRH t Address Valid After ALE Low AVLL t Address Hold After ALE Low LLAX t RD Low to Valid Data In RLDV t Data and Address Hold After RD RHDX t Data Float After RD RHDZ t ALE Low to Valid Data In ...
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... LLWL WLWH t AVWL t QVWX t LLAX t QVWH A0 A7 DATA A16 A23 V8 A15 Figure 74. External Data Memory Write Cycle Rev Page 97 of 108 ADuC845/ADuC847/ADuC848 6.29 MHz Core Clock Min Max Unit 130 ns 120 ns 135 ns 260 ns 375 ns 120 ns 250 ns 755 ns 125 ns ...
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... ADuC845/ADuC847/ADuC848 t BUF SDATA (I/O) t DSU t PSU SCLK (I) PS STOP START CONDITION CONDITION t SUP MSB LSB t DSU t DHD SHD 1 2 SUP L 2 Figure 75. I C-Compatible Interface Timing Rev Page 98 of 108 t R ACK MSB DHD RSU REPEATED ...
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... MISO DAV MSB BITS 6–1 MSB IN BITS 6– DSU DHD Figure 76. SPI Master Mode Timing (CHPA = 1) Rev Page 99 of 108 ADuC845/ADuC847/ADuC848 Min Typ Max 635 635 50 100 100 LSB ...
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... ADuC845/ADuC847/ADuC848 Table 69. SPI MASTER MODE TIMING (CPHA = 0) Parameter t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid After SCLOCK Edge DAV t Data Output Setup Before SCLOCK Edge DOSU t Data Input Setup Time Before SCLOCK Edge DSU t Data Input Hold Time After SCLOCK Edge ...
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... MISO MOSI DAV DF DR MSB BITS 6–1 BITS 6–1 MSB DSU DHD Figure 78. SPI Slave Mode Timing (CHPA = 1) Rev Page 101 of 108 ADuC845/ADuC847/ADuC848 Min Typ Max Unit 0 ns 330 ns 330 100 ns 100 ...
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... ADuC845/ADuC847/ADuC848 Table 71. SPI SLAVE MODE TIMING (CPHA = 0) Parameter SCLOCK Edge SS t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid After SCLOCK Edge DAV t Data Input Setup Time Before SCLOCK Edge DSU t Data Input Hold Time After SCLOCK Edge ...
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... QVXH t XHQX LSB BIT DVXH XHDX LSB BIT 1 Figure 80. UART Timing in Shift Register Mode Rev Page 103 of 108 ADuC845/ADuC847/ADuC848 Variable Core_Clk Max Min Typ Max 12t core t XLXL SET RI OR SET TI BIT 6 BIT 6 MSB Unit ns ns ...
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... ADuC845/ADuC847/ADuC848 OUTLINE DIMENSIONS 2.10 2.00 1.95 0.25 MIN VIEW A ROTATED 90° CCW PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE 2.45 1.03 MAX 0.88 0. SEATING PLANE 10° 6° 2° 0.23 VIEW A 0.11 PIN 1 52 7° 1 0° 0.10 COPLANARITY 0.65 BSC LEAD PITCH COMPLIANT TO JEDEC STANDARDS MO-112-AC-1 Figure 81. 52-Lead Metric Quad Flat Package [MQFP] ...
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... ADuC848BS8-3 −40°C to +125°C ADuC848BCP62-5 −40°C to +85°C ADuC848BCP62-3 −40°C to +85°C ADuC848BCP8-5 −40°C to +85°C ADuC848BCP8-3 −40°C to +85°C 2 ADuC848BSZ62-5 −40°C to +125°C ADuC848BSZ62-3 2 −40°C to +125°C ADuC845/ADuC847/ADuC848 Package Description ...
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... ADuC848BSZ32-3 −40°C to +125°C 2 ADuC848BSZ8-5 −40°C to +125°C 2 ADuC848BSZ8-3 −40°C to +125°C 2 ADuC848BCPZ62-5 −40°C to +85°C 2 ADuC848BCPZ62-3 −40°C to +85°C 2 ADuC848BCPZ8-5 −40°C to +85°C ADuC848BCPZ8-3 2 −40°C to +85°C EVAL-ADuC845QS 3 EVAL-ADuC845QSP EVAL-ADuC847QS ...
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... NOTES ADuC845/ADuC847/ADuC848 Rev Page 107 of 108 ...
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... ADuC845/ADuC847/ADuC848 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips Rights to use these components system, provided that the system conforms to the © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...