ak4396 AKM Semiconductor, Inc., ak4396 Datasheet
ak4396
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ak4396 Summary of contents
Page 1
... AC coupling capacitors and increasing performance for systems with excessive clock jitter. The AK4396 accepts 192kHz PCM data and 1-bit DSD data, ideal for a wide range of applications including DVD-Audio and SACD. The AK4396 has a fully functional compatibility with the AK4393/4/5 and lower power dissipation. • ...
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... CCLK CDTI P/S MS0336-E-00 VCOM 8X Interpolator PCM Data 8X Interpolator DSD Data Interface De-emphasis Clock Divider MCLK DEM0 Block Diagram - 2 - PDN TTL SMUTE DFS0 ΔΣ SCF Modulator ΔΣ SCF Modulator Control DEM1 VREFH VREFL [AK4396] DZFL AOUTL+ AOUTL- AOUTR+ AOUTR- DZFR 2004/08 ...
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... ASAHI KASEI Ordering Guide −40 ∼ +85°C AK4396VF AKD4396 Evaluation Board for AK4396 Pin Layout DVSS DVDD MCLK PDN BICK/DCLK SDATA/DSDL LRCK/DSDR SMUTE/CSN DFS0/CAD0 DEM0/CCLK DEM1/CDTI DIF0/DCLK DIF1/DSDL DIF2/DSDR MS0336-E-00 28pin VSOP (0.65mm pitch Top View ...
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... Linear CAD0/1 CAD0/1 32k, 44.1k, 48k 32k, 44.1k, 48k Slow Roll-off Slow Roll-off DZFL/R DZFL/R No Yes BVSS TTL DZFL DZFL DZFR DZFR AK4396 DVSS DVDD MCLK PDN BICK SDATA LRCK SMUTE/CSN DFS0/CAD0 DEM0/CCLK DEM1/CDTI DIF0 DIF1 DIF2 TTL VREFL VFEFH AVDD ...
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... DIF2 DIF1 DIF0 DFS0 DEM1 DEM0 0 DZFB 0 ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 DIF2 DIF1 DIF0 DFS0 DEM1 DEM0 0 DZFB 0 ATT3 ATT2 ATT1 ATT3 ATT2 ATT1 [AK4396] D0 RSTN SMUTE 0 ATT0 ATT0 D0 RSTN SMUTE 0 ATT0 ATT0 D0 RSTN SMUTE 0 ATT0 ATT0 2004/08 ...
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... Digital Power Supply Pin, 3.3V or 5.0V Master Clock Input Pin Power-Down Mode Pin When at “L”, the AK4396 is in power-down mode and is held in reset. The AK4396 should always be reset upon power-up. Audio Serial Data Clock Pin in PCM mode DSD Clock Pin in DSD mode ...
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... Lch Zero Input Detect Pin in serial mode Test 2 Pin in parallel mode Chip Address 1 Pin in serial mode Master Clock Auto Setting Mode Pin in parallel mode Rch Zero Input Detect Pin in serial mode - 7 - [AK4396] (Internal pull-up pin) (Internal pull-up pin) (Don’t Care) (Internal pull-down pin) (Internal pull-down pin) ...
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... These pins should be open. Setting These pins should be open. These pins should be open. These pins should be connected to DVSS. These pins should be open. Setting These pins should be open. These pins should be open. These pins should be connected to DVSS. These pins should be open [AK4396] 2004/08 ...
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... ABSOLUTE MAXIMUM RATINGS Symbol min −0.3 AVDD −0.3 DVDD Δ GND ( Note 2) IIN −0.3 VIND −40 Ta −65 Tstg Symbol min AVDD 4.75 DVDD 3.0 VREFH AVDD-0.5 VREFL AVSS Δ VREF 3 [AK4396] max 6.0 6.0 0.3 - ±10 - DVDD+0.3 85 150 typ max 5.0 5.25 5.0 5.25 - AVDD - - - AVDD Units °C ° ...
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... Note 13. PSR is applied to AVDD, DVDD with 1kHz, 100mVpp. VREFH pin is held +5V. MS0336-E-00 ANALOG CHARACTERISTICS min 0dBFS −60dBFS 0dBFS −60dBFS 0dBFS −60dBFS −60dBFS (Note 6) 114 (Note 7) 114 100 (Note 8) ±2.65 (Note 9) (Note 10) 1 (Note 11) (Note 12) (Note 13 [AK4396] ≥ 1kΩ; L typ max Units 24 Bits −100 −90 dB − − − − − − ...
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... Symbol min PB 0 −6.0dB - (Note 14 (Note 15 Symbol min PB 0 −6.0dB - (Note 14) SB 105 (Note 15 [AK4396] typ max Units 20.0 kHz 22.05 - kHz kHz ±0.005 1/fs ±0 typ max Units 43.5 kHz 48.0 - kHz kHz ±0.005 1/fs ± ...
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... PB 0 −3.0dB - (Note 15 (Note 14 Symbol min PB 0 −3.0dB - (Note 16) SB 171 (Note 15 [AK4396] typ max Units 8.1 kHz 18.2 - kHz kHz ±0.005 1/fs +0/− typ max Units 17.7 kHz 39.6 - kHz kHz ±0.005 ...
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... MS0336-E-00 Symbol min VIH 70%DVDD VIL - VOH DVDD−0.5 VOL - (Note 17) Iin - Symbol min (TTL pin) VIH 70%DVDD VIH 2.2 (TTL pin) VIL - VIL - VOH DVDD-0.5 VOL - (Note 17) Iin - - 13 - [AK4396] typ max Units - - V - 30%DVDD 0.5 V ±10 μA - typ max Units - - 30%DVDD V - 0.8 V ...
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... Note 19. BICK rising edge must not occur at the same time as LRCK edge. Note 20. DSD data transmitting device must meet this time. Note 21. The AK4396 can be reset by bringing PDN pin “L” to “H”. When the states of or DFS1-0 bits change, the AK4396 should be reset by RSTN bit. ...
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... LRCK BICK tBCKH LRCK tBLR BICK SDATA MS0336-E-00 1/fCLK tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs tBCK tBCKL Clock Timing tLRB tSDS tSDH Audio Interface Timing (PCM Mode [AK4396] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 2004/08 ...
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... Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”) CSN tCSS CCLK CDTI MS0336-E-00 tDCK tDCKL tDCKH tDDD tDCK tDCKL tDCKH tDDD tDDD tCCKL tCCKH tCDS tCDH C1 C0 R/W WRITE Command Input Timing - 16 - [AK4396] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH A4 VIL 2004/08 ...
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... ASAHI KASEI CSN CCLK CDTI D3 PDN MS0336-E- WRITE Data Input Timing tPD Power Down & Reset Timing - 17 - [AK4396] tCSW VIH VIL tCSH VIH VIL VIH D0 VIL VIL 2004/08 ...
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... PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode, PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode changes by D/P bit, the AK4396 should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4396 performs for only PCM data. ...
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... MCLK frequency is detected automatically and the sampling speed is set by DFS1-0 bits (Table 6). The MCLK frequency corresponding to each sampling speed should be provided (Table 7). The AK4396 is set to Manual Setting Mode at power-up (PDN pin = “L” → “H”). When DFS1-0 bits are changed, the AK4396 should be reset by RSTN bit. DFS1 bit ...
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... If these clocks are not provided, the AK4396 may draw excess current because the device utilizes dynamic refreshed logic internally. The AK4396 should be reset by PDN pin = “L” after threse clocks are provided. If the external clocks are not present, the AK4396 should be in the power-down mode (PDN pin = “L”). After exiting reset(PDN pin = “ ...
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... Figure 1 ≥ 48fs Figure 2 ≥ 48fs Figure 3 Default ≥ 48fs Figure 4 ≥ 48fs Figure Rch Data Rch Data [AK4396 2004/08 ...
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... Don’t care 23 Lch Data Figure 4. Mode 3 Timing Figure 5. DSD Mode Timing - Don’t care 1 Rch Data Don’t care Rch Data [AK4396 2004/08 ...
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... Table 12. De-emphasis Control (Normal Speed Mode) Output Volume The AK4396 includes channel independent digital output volumes (ATT) with 256 levels at linear step including MUTE. These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing levels, transitions are executed via soft changes ...
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... DZF pin immediately goes to “L” if input data are not zero after going DZF pin “H”. System Reset The AK4396 should be reset once by bringing PDN pin = “L” upon power-up. The analog section exits power-down mode by MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during 4/fs ...
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... ASAHI KASEI Power-Down The AK4396 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z). Figure 9 shows an example of the system timing at the power-down and power-up. PDN Internal Normal Operation State D/A In (Digital) D/A Out (Analog) Clock In MCLK, BICK, LRCK ...
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... Reset Function When RSTN bit = “0”, the AK4396’s digital section is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage and DZF pins of both channels go to “H”. Figure 10 shows the example of reset by RSTN bit ...
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... When the state of P/S pin is changed, the AK4396 should be reset by PDN pin. The serial control interface is enabled by the P/S pin = “L”. In this mode, pin setting must be all “L”. Internal registers may be written by 3-wire µP interface pins: CSN, CCLK and CDTI. The data on this interface consists of Chip address (2bits, CAD0/1), Read/Write (1bit ...
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... RSTN: Internal timing reset 0 : Reset. All registers are not initialized Normal Operation (Default) When the states of DFS1-0 bits change, the AK4396 should be reset by PDN pin or RSTN bit. DIF2-0: Audio data interface modes (see Initial value is “010” (Mode 2: 24bit MSB justified). ...
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... Enable Zero detect function can be disabled by DZFE bit “0”. In this case, the DZF pins of both channels are always “L”. MS0336-E- DZFE DZFM SLOW DFS1 Table 12) Table DFS0 DEM1 DEM0 [AK4396] D0 SMUTE 0 2004/08 ...
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... DSDM: DSD Input Select 0 : Input pin : No. (Default Input pin : No. 12, 13, 14 When DSDM bit is changed, the AK4396 should be reset by RSTN bit. D/P: DSD/PCM Mode Select 0 : PCM mode (Default DSD mode When D/P bit is changed, the AK4396 should be reset by RSTN bit. ...
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... AOUTL LRCK AOUTL- 22 CSN 8 AOUTR+ 21 AOUTR- 9 CAD0 20 10 CCLK AVSS 19 0.1u CDTI 11 AVDD 18 12 DIF0 VREFH 17 0.1u VREFL 16 13 DIF1 DIF2 14 TTL [AK4396] 10u 0.1u + Lch Lch Lch Out LPF Mute Rch Rch Rch Out LPF Mute 10u + Analog Supply 5V + 10u 2004/08 ...
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... BICK VCOM AK4396 SDATA 6 AOUTL+ 7 LRCK AOUTL- 8 SMUTE AOUTR+ AOUTR- 9 DFS0 10 DEM0 AVSS 11 DEM1 AVDD DIF0 12 VREFH 13 VREFL DIF1 DIF2 P/S 25 10u 0. Lch Lch Out LPF 22 Rch 21 Rch Out LPF 20 19 0.1u 10u + 18 Analog 17 Supply 5V + 0.1u 10u 16 TTL 15 [AK4396] 2004/08 ...
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... Rch Rch Out LPF Mute 10u + Analog Supply 5V + 10u 1 DVSS DZFR 28 2 DVDD CAD1 27 3 MCLK DZFL 26 PDN 4 P BICK VCOM 24 AK4396 6 SDATA AOUTL LRCK AOUTL- 22 CSN 8 AOUTR CAD0 AOUTR CCLK AVSS 19 CDTI 11 AVDD 18 12 DIF0 VREFH 17 13 ...
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... VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREFH, VREFL and VCOM pins in order to avoid unwanted coupling into the AK4396. 3. Analog Outputs The analog outputs are full differential outputs and 2.8Vpp (typ, VREFH − VREFL = 5V) centered around VCOM. The differential outputs are summed externally, V summing gain is 1, the output range is 5.6Vpp (typ, VREFH − ...
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... Table 16. Filter Response of External LPF Circuit Example 2 for PCM MS0336-E-00 + 10u 0.1u 6 10u + 0.1u + 10u 0.1u 6 10u + 0. Stage 2 Stage 182kHz 284kHz 0.637 +3.9dB -0.88dB 20kHz -0.025 -0.021 40kHz -0.106 -0.085 80kHz -0.517 -0.331 - 35 - +15 -15 10u 0.1u + 560 1.0n 100 620 620 7 1.0n NJM5534D + 10u 0.1u Total - - - +3.02dB -0.046dB -0.191dB -0.848dB [AK4396] Lch 2004/08 ...
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... It is recommended by SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass filter with a cut-off frequency of maximum 50kHz and a slope of minimum 30dB/Oct. The AK4396 can achieve this filter response by combination of the internal filter (Table 17) and an external filter (Figure 18). ...
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... Seating Plane NOTE: Dimension "*" does not include mold flash. Material & Lead finish Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate MS0336-E-00 PACKAGE 15 14 0.65 Detail [AK4396] 1.25 ± 0.2 A +0.1 0.15-0.05 0.1 ± 0.1 0-10 ° 2004/08 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0336-E-00 MARKING AKM AK4396VF XXXBYYYYC XXXXBYYYYC: Date code identifier Lot number (X : Digit number Alpha character ) Assembly date (Y : Digit number C : Alpha character) Revision History Reason Page Contents First Edition IMPORTANT NOTICE - 38 - [AK4396] 2004/08 ...