ak4524 AKM Semiconductor, Inc., ak4524 Datasheet
ak4524
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ak4524 Summary of contents
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... ASAHI KASEI The AK4524 is a high performance 24bit CODEC for the 96kHz recording system. The ADC has an Enhanced Dual Bit architecture with wide dynamic range. The DAC uses the new developed Advanced Multi Bit architecture and achieves low outband noise and high jitter tolerance by use of SCF (switched capacitor filter) techniques ...
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... AINR VCOM AOUTL+ AOUTL- AOUTR+ AOUTR- VREF Control Register I/F VA AGND CS CCLK M0050-E-03 ADC HPF DATT DATT DAC SMUTE Clock Gen. & Divider CDTI CIF CLKO XTO XTI Block Diagram - 2 - [AK4524 DGND PD LRCK BICK Audio I/F SDTO Controller SDTI M/ S XTALE 2004/01 ...
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... XTI XTALE LRCK BICK SDTO SDTI M0050-E-03 −20 ∼ +85°C 28pin VSOP (0.65mm pitch) Evaluation Board AK4524 6 Top 7 View [AK4524] 28 AOUTR+ 27 AOUTR- 26 AOUTL+ 25 AOUTL- 24 DGND CLKO CIF CCLK 15 CDTI ...
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... Lch Negative Analog Output Pin 26 AOUTL+ O Lch Positive Analog Output Pin 27 AOUTR− O Rch Negative Analog Output Pin 28 AOUTR+ O Rch Positive Analog Output Pin Note: All input pins except pull-down pins should not be left floating. M0050-E-03 PIN/FUNCTION Function (Internal pull-down pin [AK4524] 2004/01 ...
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... M0050-E-03 ABSOLUTE MAXIMUM RATINGS Symbol min −0.3 VA −0.3 VD −0.3 VT VDA - IIN - −0.3 VINA −0.3 VIND −20 Ta −65 Tstg Symbol min VA 4.75 VD 4.75 VT 2.7 VREF 3 [AK4524] max Units 6.0 V 6.0 V 6.0 V 0.3 V ±10 mA VA+0.3 V VA+0.3 V °C 85 °C 150 typ max Units 5.0 5. ...
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... M0050-E-03 ANALOG CHARACTERISTICS min (Note 3) 2 (Note 104 96 104 96 100 (Note 5) 5.0 (In case of AC load) 1 (In case of AC load [AK4524] typ max Units 2.9 3.1 Vpp 10 15 kΩ 0.5 0 Bits 100 100 105 dB 0 ...
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... M0050-E-03 min (fs=44.1kHz) (fs=96kHz) (Note 6) FILTER CHARACTERISTICS Symbol min 24. ∆ 24 [AK4524] typ max Units µA 10 100 µA 10 100 typ max Units 19.76 kHz 20.02 - kHz 20.20 - kHz 22.05 - kHz kHz ±0.005 ...
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... S mode) tLRS tBSD tSDH 20 tSDS 20 fBCK dBCK tMBLR -20 tBSD -20 tSDH 20 tSDS [AK4524] typ Max Units - - 0.5 V ±10 µA - typ max Units 24.576 MHz 49.152 MHz ns ns 24.576 MHz kHz ...
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... CCLK “↑” “↓” Reset Timing PD Pulse Width (Note 12) RSTAD “↑” to SDTO valid (Note 13) Note: 12. The AK4524 can be reset by bringing PD “L”. 13. These cycles are the number of LRCK rising from RSTAD bit. M0050-E-03 Symbol min ...
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... BICK tBCKH CLKO LRCK tBLR BICK tLRS SDTO SDTI M0050-E-03 1/fCLK tCLKL 1/fs tBCK tBCKL tH tL dMCK=tH/(tH+tL) or tL/(tH+tL) Clock Timing tLRB tSDS tSDH Audio Interface Timing (Slave mode [AK4524] VIH VIL VIH VIL VIH VIL 50%VT VIH VIL VIH VIL tBSD 50%VT VIH VIL 2004/01 ...
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... Audio Interface Timing (Master mode) tCCKL tCCKH tCDS tCDH C1 C0 R/W WRITE Command Input Timing WRITE Data Input Timing tPD Power Down & Reset Timing - 11 - [AK4524] 50%VT 50%VT tBSD 50%VT VIH VIL VIH VIL VIH VIL VIH VIL VIH A4 VIL tCSW VIH ...
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... Table 1. Sampling Speed MCLK Normal speed Double speed (DFS1-0 = “00”) (DFS1-0 = “01”) 256fs N/A 512fs 256fs 1024fs 512fs 384fs N/A 768fs 384fs Table 2. Master Clock Frequency Select - 12 - [AK4524] at reset - - 4 times speed (DFS1-0 = “10” or “11”) at reset N/A 128fs 256fs N/A 192fs 2004/01 ...
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... Don’t Care Figure 1. Mode 0 Timing - 13 - [AK4524] fs=88.2kHz fs=96kHz N/A N/A 22.5792MHz 24.576MHz 45.1584MHz 49.152MHz N/A N/A 33.8688MHz 36.864MHz LRCK BICK ≥ 32fs H/L ≥ 40fs H/L ≥ 48fs at reset H/L ≥ 48fs L/H ≥ 48fs H/L ...
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... Don’t Care Lch Data Figure 4. Mode 3 Timing Don’t Care Figure 5. Mode 4 Timing - 14 - [AK4524 Rch Data ...
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... ASAHI KASEI Input Volume The AK4524 includes two channel independent analog volumes (IPGA) with 37 levels, 0.5dB step in front of ADC and digital volumes (IATT) with 128 levels (including MUTE) after ADC. The control data of both volumes are assigned in the same register address. When MSB of the register is “1”, the IPGA changes and the IATT changes at MSB “0”. ...
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... Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB. M0050-E-03 DEM1 DEM0 Mode 0 0 44.1kHz 0 1 OFF 1 0 48kHz 1 1 32kHz 1024/fs ( (2) Figure 6. Soft Mute - 16 - [AK4524] at reset ( 2004/01 ...
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... Power Down & Reset The ADC and DAC of AK4524 are placed in the power-down mode by bringing a power down pin, PD “L” and each digital filter is also reset at the same time. The internal register values are initialized by PD “L”. This reset should always be done after power-up. And then as both control registers of ADC and DAC go reset state (RSTAD=RSTDA=“ ...
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... Normal operation XTAL = Oscillation CLKO = Output LRCK = Output BICK = Output Shut off Inhibit XTI = MCLK in XTO = L CLKO = L LRCK = H BICK = [AK4524] XTALE Power down XTAL = Oscillation CLKO = Output LRCK = Input BICK = Input Inhibit XTALE Power down XTAL = Oscillation CLKO = Output ...
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... DIF2 DIF1 DIF0 CMODE 0 0 ZCEI IPGL6 IPGL5 IPGL4 IPGR6 IPGR5 IPGR4 0 ATTL6 ATTL5 ATTL4 0 ATTR6 ATTR5 ATTR4 - 19 - [AK4524 PWVR PWAD PEDA 0 0 RSTAD RSTDA CKS1 CKS0 DFS1 DFS0 ZTM1 ZTM0 DEM1 DEM0 IPGL3 IPGL2 IPGL1 IPGL0 IPGR3 ...
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... ASAHI KASEI Control Register Setup Sequence When PD pin goes “L” to “H” upon power-up etc., the AK4524 should operate by the next sequence. In this case, all control registers are set to initial values and the AK4524 is in the reset state. (1) Set the clock mode and the audio data interface mode. ...
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... Initial: 24bit MSB justified for both ADC and DAC M0050-E- DIF2 DIF1 DIF0 CMODE [AK4524 RSTAD RSTDA CKS1 CKS0 DFS1 DFS0 2004/01 ...
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... But the ADCs output “0” during first 516 cycles. M0050-E- ZCEI IPGL6 IPGL5 IPGL4 IPGR6 IPGR5 IPGR4 [AK4524 ZTM1 ZTM0 DEM1 DEM0 IPGL3 IPGL2 IPGL1 IPGL0 IPGR3 IPGR2 IPGR1 IPGR0 ...
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... DATT=2 33) – 33 −17.90 0.53 −18.32 m: MSB 3-bits of data 0.42 −18.61 l: LSB 4-bits of data 0. −24.20 0.54 −24.64 0.43 −24.94 0. −30.82 0.58 −31.29 0.46 −31.61 0. −38.18 0.67 −38.73 0.54 −39.11 0. −47.73 0.99 −48.55 0.83 −49.15 0. −58.10 1.58 −60.03 1.94 −62.53 2.50 −66.05 3.52 −72.07 6.02 MUTE Table 10. IPGA code table - 23 - [AK4524] IPGA Analog volume with 0.5dB step IATT 2004/01 ...
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... Refer to Table 11 Initial: 7FH (0dB) The AK4524 includes digital ATT with 128 levels equivalent to ADC’s. The OATTs are set to “00H” when PD pin goes “L”. After returning to “H”, the OATTs fade in the initial value, “7FH” by 8031 cycles. ...
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... DATAs. −12.43 0. DATT=2 33) – 33 −17.90 0.53 −18.32 0.42 m: MSB 3-bits of data −18.61 l: LSB 4-bits of data 0. −24.20 0.54 −24.64 0.43 −24.94 0. −30.82 0.58 −31.29 0.46 −31.61 0. −38.18 0.67 −38.73 0.54 −39.11 0. −47.73 0.99 −48.55 0.83 −49.15 0. −58.10 1.58 −60.03 1.94 −62.53 2.50 −66.05 3.52 −72.07 6.02 MUTE Table 11. OATT code table - 25 - [AK4524] OATT 2004/01 ...
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... ASAHI KASEI Figure 10 & Figure 11 show the system connection diagram. This is an example which the AK4524 operates at X’tal mode. In case of external clock mode, please refer to Figure 11. An evaluation board (AKD4524) is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. ...
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... power supply pin to interface with the external ICs and is supplied from digital supply in system. AGND and DGND of the AK4524 should be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4524 as possible, with the small value ceramic capacitor being the nearest ...
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... The DC offset including ADC own DC offset removed by the internal HPF. The AK4524 samples the analog inputs at 64fs. The digital filter rejects noise above the stopband except for multiples of 64fs. The AK4524 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. ...
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... Figure 14. External low cost 1st order LPF Example (using dual supply op-amp) Peripheral I/F Example The digital inputs of the AK4524 are TTL inputs and can accept the signal of device with a nominal 3V supply. The digital output can interface with the peripheral device with a nominal 3V supply when the VT supply operates at a nominal 3V supply ...
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... Seating Plane NOTE: Dimension "*" does not include mold flash. Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: M0050-E-03 PACKAGE 0.65 Detail A | 0.10 Epoxy Cu Solder plate - 30 - [AK4524] 1.25±0.2 +0.1 0.15-0.05 0.1±0.1 0-10° 2004/01 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. M0050-E-03 MARKING AKM AK4524VF XXXBYYYYC XXXBYYYYC: Date code identifier IMPORTANT NOTICE - 31 - [AK4524] 2004/01 ...