AN983 ETC [List of Unclassifed Manufacturers], AN983 Datasheet

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AN983

Manufacturer Part Number
AN983
Description
PCI/miniPCI-to-Ethernet LAN Controller
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet

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ADMtek
AN983B/AN983BL
PCI/miniPCI-to-Ethernet LAN
Controller
DATASHEET
Rev. 1.8
MAY. 2003
Information in this document is provided in connection with ADMtek products. ADMtek may make changes to specifications
and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features
or instructions marked "reserved" or "undefined." ADMtek reserves these for future definition and shall have no responsibility
whatsoever for conflicts or incompatibilities arising from future changes to them.
The products may contain design defects or errors known as errata, which may cause the product to deviate from published
specifications. Current characterized errata are available on request. To obtain latest documents, please contact your local
ADMtek sales office or your distributor or visit ADMtek’s website at http://www.ADMtek.com.tw
*Third-party brands and names are the property of their respective owners.
.com.tw

Related parts for AN983

AN983 Summary of contents

Page 1

... AN983B/AN983BL PCI/miniPCI-to-Ethernet LAN Controller DATASHEET Rev. 1.8 MAY. 2003 ADMtek .com.tw Information in this document is provided in connection with ADMtek products. ADMtek may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." ADMtek reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them ...

Page 2

... AN983B Datasheet Revision History Revision Date Revision 0.1 Oct, 2000 1.0 Feb, 2001 1.1 Mar, 2001 1.2 Sep, 2001 1.3 Sep, 2001 1.4 Sep, 2001 1.5 JULY, 2002 1.6 JULY, 2002 1.7 JULY, 2002 1.8 MAY, 2003 Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY Description Draft data sheet for review First release Add CSR15 ...

Page 3

... PIN ASSIGNMENT DIAGRAM............................................................................... 14 6. PIN DESCRIPTION................................................................................................... 15 7. REGISTERS AND DESCRIPTORS DESCRIPTION............................................ 19 7.1 AN983B configuration registers ......................................................................... 20 7.1.1. AN983B configuration registers list ....................................................... 20 7.1.2. AN983B configuration registers table .................................................... 21 7.1.3 AN983B configuration registers descriptions.......................................... 22 CR0 (offset = 00h), LID - Loaded Identification number of Device and Vendor ........................................................................................................................... 22 CR1 (offset = 04h), CSC - Configuration command and status ....................... 22 CR2 (offset = 08h Class Code and Revision Number ...

Page 4

... CR13 (offset = 34h Capabilities Pointer. ............................................... 25 CR15 (offset = 3ch Configuration Interrupt............................................ 25 CR16 (offset = 40h Driver Space for special purpose. .......................... 25 CR32 (offset = 80h), SIG - Signature of AN983B ........................................... 25 CR48 (offset = c0h), PMR0, Power Management Register0............................ 26 CR49 (offset = c4h), PMR1, Power Management Register 1........................... 26 7.2. PCI Control/Status registers.............................................................................. 28 7 ...

Page 5

... AN983B CSR26 (offset = a8h) - PAR1, physical address register 1............................... 44 CSR27 (offset = ach) - MAR0, multicast address register 0 ............................ 45 CSR28 (offset = b0h) - MAR1, multicast address register 1............................ 45 Operation Mode Register (Memory base offset 0FCh) .................................... 46 7.3. PHY Registers (ACCESSED by csr9 MDI/MMC/MDO/MDC) ......................... 47 7.3.1. Transceiver registers Descriptions .......................................................... 47 7.4. Descriptors and Buffer Management................................................................. 51 7 ...

Page 6

... Timing Specifications........................................................................................ 79 PCI Clock Specifications .................................................................................. 79 PCI Timings ...................................................................................................... 80 Flash Interface Timings .................................................................................... 81 EEPROM Interface Timings (AC/AD)............................................................. 83 11. PACKAGE................................................................................................................. 87 Dimensions for 128 –pin PQFP Package(AN983B)......................................... 87 Dimensions for 128 –pin LQFP Package(AN983BL) ...................................... 88 12. LAYOUT GUIDE (REV.1.0B) Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY .................................................................................. 89 ADMtek Inc. ...

Page 7

... AN983B Layout Guide Revision History: ....................................................................... 89 12.1 placement .......................................................................................................... 89 12.2 trace routing...................................................................................................... 89 12.3 Vcc and GND .................................................................................................... 90 Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY ADMtek Inc. www.admtek.com.tw 7 ...

Page 8

... AN983B FIGURE INDEX Fig - 1 System diagram of the AN983B ...................................................................................10 Fig - 2 Block diagram of the AN983B .....................................................................................13 Fig - 3 Pin assignment ..............................................................................................................14 Fig - 4 Initializatin flow............................................................................................................56 Fig - 5 Ring structure of frame buffer ......................................................................................57 Fig - 6 Chain structure of frame buffer.....................................................................................58 Fig - 7 Transmit pointers for descriptor management ..............................................................59 Fig - 8 Receive pointers for descriptor management................................................................60 Fig - 9 Transmit flow ...

Page 9

... IEEE802.3u and 10BASE-T of IEEE802.3. The auto-negotiation function is also supported for speed and duplex detection. The AN983B can be programmed as MAC-only controller. In this mode, it provides the standard MII interface to link to an external PHY. With this mode, it can be connected to the HomePNA PHY to support the HomePNA networking solution or Homeplug Phy(Power-line solution) to support Homeplug networking solution ...

Page 10

... AN983B 2. SYSTEM BLOCK DIAGRAM EEPROM AN983B 25MHz Crystal Fig - 1 System diagram of the AN983B Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY Boot ROM LEDs ADMtek Inc. www.admtek.com.tw RJ-45 10 ...

Page 11

... AN983B 3. FEATURES INDUSTRY STANDARD IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant Support for IEEE802.3x flow control IEEE802.3u Auto-Negotiation support for 10BASE-T and 100BASE-TX PCI Specification 2.2 compliant ACPI and PCI power management Ver.1.1 compliant Support PC99 wake on LAN FIFO Provides two independent long FIFOs with 2k bytes each for transmission and receiving Pre-fetch up to two transmit packets to minimize inter frame gap (IFG ...

Page 12

... AN983B Provides serial interface for read/write 93C46/66 EEPROM Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency, and Minimum-Grand from the 64 byte contents of 93C46/66 after PCI reset de-asserted in PCI environment. MAC/PHYSICAL Integrates the whole Physical layer functions of 100BASE-TX and 10BASE-T Provides Full -duplex operation on both 100Mbps and 10Mbps modes ...

Page 13

... I/F T ran sit C on trol B oot ontrol I eive I/F Fig - 2 Block diagram of the AN983B Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY ontrol T ransm ...

Page 14

... PIN ASSIGNMENT DIAGRAM 1 bra 13 2 bra 14 3 bra 15 4 VAAR 5 TST3 6 RXIN 7 RXIP 8 GNDR 9 TST0 10 TST1 11 TST2 GNDREEF 15 RIBB 16 VAAREF 17 XTLN 18 XTLP AN983B/AN983BL 19 GNDT 20 TXOP 21 TXON 22 VAAT 23 Vdd-IR 24 INTA# 25 RST# 26 Vss-IR 27 pci_clk 28 Vdd-pci 29 gnt# 30 req# 31 pme# 32 Vss-pci 33 AD31 34 AD30 35 AD29 36 AD28 ...

Page 15

... I/O The Power Management Event signal is an open drain, active low signal. When WOL-bit 18 of CSR 18 be set into “1”, means that the AN983B is set into Wake On LAN mode. Packet frame from network then the AN983B will active this signal too. ...

Page 16

... Clk-run I/O Clock Run for PCI system. In the normal operation situation, Host should assert this signal to indicate AN983B about the normal situation. On the O/D other hand, when Host will deassert this signal when the clock is going down to a non-operating frequency. When AN983B recognizes the deasserted status of clk-run, then it will assert clk-run to request host to maintain the normal clock operation ...

Page 17

... AN983B 115 BrWE# O BootROM Write Enable for flash ROM application. MII INTERFACE (PROGRAM AN983B AS MAC-ONLY MODE, SET FCH [2:0] = 100B) 127 Mdc O MII Management Data Clock 126 Mtxen O MII Transmit Enable 109,110 MtxD0~3 O MII Transmit Data 112,113 108 Mtxerr O MII Transmit Error ...

Page 18

... AN983B will be driven on with 20 Hz blinking frequency when a collision status is detected in the half duplex configuration. 104 Led-100Lnk O 4Leds mode: LED display for 100Mb/s speed. This pin will be driven on (Led-speed) continually when the 100Mb/s network operating speed is detected. (3Leds mode): LED display for 100M b/s or 10M b/s speed. This pin will be driven on continually when the 100M b/s network operating speed is detected ...

Page 19

... AN983B. The PCI control/status registers are used to communicate between host and AN983B. Host can initialize, control, and read the status of the AN983B through the mapped I/O or memory address space. Regarding the registers of transceiver portion of AN983B, it includes 7 basic registers which are defined according to the clause 22 “ ...

Page 20

... AN983B 7.1 AN983B CONFIGURATION REGISTERS With the configuration registers software driver can initialize and configure AN983B. All of the contents of configuration registers are set to default value when there is any hardware reset occurs. On the other hand, there is no effect to their value when the software reset occurs. To access these configuration registers AN983B provides byte, word, and double word data access length ...

Page 21

... AN983B 7.1.2. AN983B CONFIGURATION REGISTERS TABLE Offset b31 ----------- 00h Device ID* 04h Status 08h Base Class Subclass Code 0ch ------ ------ 10h Base I/O address 14h Base memory address 18h~ Reserved 24h 28h ROM-im* Address space offset* 2ch Subsystem ID* 30h Boot ROM base address 34h Reserved ...

Page 22

... AN983B asserted parity error - PERR detected parity error asserted by other device. AN983B is operating as a bus master. AN983B’s parity error response bit (bit 6 of CR1) is enabled. SFBB Status of Fast Back-to-Back 23 Always 1, since AN983B has the ability to accept fast back-to-back transactions ...

Page 23

... Name Descriptions --- Reserved. 31~16 LT Latency Timer. This value specifies the latency timer of the 15~ 8 AN983B in units of PCI bus clock. Once the AN983B asserts FRAME#, the latency timer starts to count. If the latency Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY ADMtek Inc. www.admtek.com.tw 0 R/W ...

Page 24

... Name Descriptions BRBA Boot ROM Base Address. This value indicates the address 31~17 mapping of boot ROM field. Besides, it also defines the boot ROM size. The value of bit 17~10 is set to 0 for AN983B supports up to 256KB of boot ROM. --- Reserved Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY ADMtek Inc ...

Page 25

... Bit # Name Descriptions ML Max_Lat register. This value indicates “how often” the 31~24 AN983B needs to access to the PCI bus in the units of 250ns. This value is loaded from serial EEPROM after power on or hardware reset. MG Min_Gnt register. This value indicates how long the AN983B 23~16 needs to retain the PCI bus ownership whenever it initiates a transaction, in the units of 250ns ...

Page 26

... PME_Status, This bit is set when the AN983B would normally 15 assert the PME# signal for wake-up event, this bit is independent of the state of the PME-En bit. Writing a “1” to this bit will clear it and cause the AN983B to stop asserting a PME# (if enabled). Writing a “0” has no effect. DSCAL ...

Page 27

... PME_En is set or not. --- Reserved. 7~2 PWRS PowerState, This two-bit field is used both to determine the 1,0 current power state of the AN983B and to set the AN983B into a new power state. The definition of this field is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot This field is auto cleared to D0 when power resumed ...

Page 28

... AN983B 7.2. PCI CONTROL/STATUS REGISTERS 7.2.1. PCI CONTROL/STATUS REGISTERS LIST Offset from Index Name base address of CSR CSR0 PAR 00h CSR1 TDR 08h CSR2 RDR 10h CSR3 RDB 18h CSR4 TDB 20h CSR5 SR 28h CSR6 NAR 30h CSR7 IER 38h CSR8 LPC 40h ...

Page 29

... MRLE Memory Read Line Enable enable AN983B to generate memory read line command, while read access instruction reach the cache line boundary. If the read access instruction doesn’t reach the cache line boundary then AN983B uses the memory read command instead ...

Page 30

... SWR Software reset 0 1: reset all internal hardware, except configuration registers. This signal will be cleared by AN983B itself after it completed the reset process. R/W* = before writing the transmit and receive operations should be stopped. CSR1 (offset = 08h), TDR - Transmit demand register Bit # ...

Page 31

... FBE Fatal Bus Error while any of parity error, master abort, or target abort is occurred (see bits 25~23 of CSR5). AN983B will disable all bus access. The way to recover parity error is by setting software reset. Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY ADMtek Inc. ...

Page 32

... AN983B. The transmission process is suspended in this situation. To restart the transmission process, the ownership bit of next transmit descriptor should be set to AN983B and if the transmit automatic polling is not enabled then a transmit poll demand command should be issued. ...

Page 33

... Reserved 20 SQE SQE Disable 19 0: enable SQE function for 10BASE-T operation. The AN983B provides SQE test function for 10BASE-T half duplex operation. 1: disable SQE function. ----- Reserved 18~16 TR Transmit threshold control 15~14 00: 128-byte (100Mbps), ...

Page 34

... AN983B 0: filters all bad packets --- Reserved 2 SR Start/Stop Receive 1 0: receive processor will enter stop state after the current reception frame completed. This value is effective only when the receive processor is in the running or suspending state. Notice: In “Stop Receive” state, the PAUSE packet and Remote Wake Up packet won’ ...

Page 35

... AN983B 1: combine this bit and bit 16 of CSR7 to enable receive completed interrupt. TUIE Transmit Under-flow Interrupt Enable 5 1: combine this bit and bit 15 of CSR7 to enable transmit under-flow interrupt. --- Reserved 4 TJTTIE Transmit Jabber Timer Time-out Interrupt Enable 3 1: combine this bit and bit 15 of CSR7 to enable transmit jabber timer time-out interrupt ...

Page 36

... Serial EEPROM data out 3 This bit serially shifts data from the EEPROM to the AN983B. SDI Serial EEPROM data in 2 This bit serially shifts data from the AN983B to the EEPROM. SCLK Serial EEPROM clock 1 High/Low this bit to provide the clock signal for EEPROM. ...

Page 37

... Wake-up Frame Received Enable. The AN983B will include 10 the “Wake-up Frame Received” event into wake-up events. If this bit is set, AN983B will assert PMES bit of PMR1 after AN983B has received a matched wake-up frame. MPRE Magic Packet Received Enable. The AN983B will include the 9 “ ...

Page 38

... AN983B 0008h 000ch 0010h CRC16 of pattern 1 0014h 0018h 001ch 0020h 0024h CRC16 of pattern 2 0028h 002ch 0030h 0034h 0038h CRC16 of pattern 3 003ch 0040h 0044h 0048h 004ch CRC16 of pattern 4 0050h 0054h 0058h 005ch 0060h CRC16 of pattern 5 1. Offset value is from 0-255 (8-bit width). ...

Page 39

... AN983B watchdog timer from last carrier deserted bit-time 1: 48 bit-time RWD Receive Watchdog Disable the receiving packet bytes, the watchdog timer will be expired. 1: disable the receive watchdog. --- Reserved 3 JCLK Jabber clock 2 0: cut off transmission after 2.6 ms (100Mbps (10Mbps). ...

Page 40

... D3cold support, mapped to CR48<31> 31 AUXCL Aux Current. These three bits report the maximum 3.3 Vaux 30-28 current requirements for AN983B. If bit 31 of PMR0 is ‘1’, the default value is 0101b, means AN983B need 100 mA to support remote wake-up in D3cold power state. PMEP Actively type select ...

Page 41

... Power Management, enables the AN983B whether to activate 19 the Power Management abilities. When this bit is set into “0” the AN983B will set the Cap_Ptr register to zero, indicating no PCI compliant power management capabilities. The value of this bit will be mapped to NC-bit 20 of CR1. ...

Page 42

... PME# signal for wakeup event, this bit is independent of the state of the PME-En bit. Writing a “1” to this bit will clear it and cause the AN983B to stop asserting a PME#(if enabled). Writing a “0” has no Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY ADMtek Inc ...

Page 43

... D3cold. --- Reserved. 7~2 PWRS PowerState, This two bit field is used both to determine the 1,0 current power state of the AN983B and to set the AN983B into a new power state. The definition of this field is given below. 00b - D0 01b - D1 10b - D2 11b - D3hot If software attempts to write an unsupported, optional state ...

Page 44

... AN983B TBCNT Transmit Burst Count 20~16 After this number of consecutive successful transmit, transmit completed interrupt will be generated. Continuously do this function if no reset. TTO Transmit Time-Out = (deferred time + back-off time). 11~0 When the TDIE (bit28 of ACSR7) is set, the timer is decreased in unit of 2.56us(100M) or 25.6us(10M). If the timer expires before another packet transmit begin, then the TDIE interrupt will be generated ...

Page 45

... MAR0 and MAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bit19-17=000). Multicast 64 Algorithm: AN983B uses CRC [5:0] to hit one of the 64 entries in UMAR1 [31:0] and MAR0[31:0] by generated CRC32 from Ethernet DA (destination address). The most significant bit CRC [5] choose the upper or lower double word, (MAR1 or MAR0), the lower 5 bit present for the corresponding bit inside the double word ...

Page 46

... LINK Network Link Status 29 1: Link On 2: Link Off Reserved 28~27 EERLOD Write 1 to this bit will cause AN983B to reload data from 26 EEPROM. After reload completed, this bit will be cleared automatically. Reserved 25~3 OpMode These three bits are used to configure AN983B’s operation ...

Page 47

... AN983B 7.3. PHY REGISTERS (ACCESSED BY CSR9 MDI/MMC/MDO/MDC) 7.3.1. TRANSCEIVER REGISTERS DESCRIPTIONS Register 0 (MII Control) BIT NAME 15 Reset 14 Loopback 13 Speed selection 12 Autonegotiation enable 11 Power down 10 Isolate 9 Restart autonegotiation 8 Duplex mode 7 Collision test 6:0 Reserved SC Self Clearing Reset Reset this port only. This will cause the following: 1 ...

Page 48

... AN983B When set inhibits actual transmission on the wire. Speed selection Forces speed of Phy only when autonegotiation is disabled. The default state of this bit will be determined by a power-up configuration pin in this case. Otherwise it defaults to 1. Auto-neg enable Defaults to pin programmed value. When cleared allows forcing of speed and duplex settings ...

Page 49

... AN983B duplex 8-7 Reserved 6 MF Preamble 1 = PHY can accept management frames Suppression with preamble suppression 0 = PHY cannot accept management frames with preamble suppression 5 Autoneg Complete 1 = autoneg completed autoneg incomplete 4 Remote Fault 1 = remote fault detected remote fault detected 3 Autoneg Ability 1 = PHY can auto-negotiate, ...

Page 50

... AN983B (bits 5-0) 3:0 PHY_ID[3-0] Revision Number (bits 3-0); Register 3, bit bit of PHY Identifier This uses the OUI of ADMtek, device type of 1 and rev 0. Register 4 BIT NAME DESCRIPTION 15 Next Page 1 = Device set to use Next Page Device not set to use Next Page 14 Reserved 13 Remote Fault ...

Page 51

... AN983B The contents of this register should not be relied upon unless register 1 bit 5 is set (autoneg complete). After negotiation this register should contain a copy of the link partner’s register 4. All bits are therefore defined in the same way as for register 4. All bits are read only. ...

Page 52

... AN983B The AN983B provides receive and transmit descriptors for packet buffering and management. 7.4.1 RECEIVE DESCRIPTOR RDES0 Own RDES1 --- Control RDES2 RDES3 Descriptors and receive buffers addresses must be longword alignment 7 ...

Page 53

... AN983B FS First descriptor Last descriptor Too long packet (packet length > 1518 bytes). This bit is valid only in last descriptor 7 CS Late collision. Set when collision is active after 64 bytes. This bit is valid only in last 6 descriptor FT Frame type. This bit is valid only in last descriptor. ...

Page 54

... AN983B Own Status TDES0 Control TDES1 Buffer1 address TDES2 Buffer2 address TDES3 Descriptor addresses must be longword alignment TDES0 Bit # Name Descriptions OWN Own bit ...

Page 55

... AN983B TER End of Ring 25 TCH 2nd address chain 24 Indicate the buffer2 address is the next descriptor address DPD Disable padding function 23 --- Reserved 22 TBS2 Buffer 2 size 21-11 TBS1 Buffer 1 size 10-0 TDES2 Bit # Name Descriptions BA1 Buffer Address 1. Without any limitation on the transmission buffer address. ...

Page 56

... AN983B 8. FUNCTIONAL DESCRIPTIONS 8.1 INITIALIZATION FLOW The flow of initialize AN983B is shown as below. Need setting media type? Read EEPROM from CSR9 Set Physical address (CSR25, 26) Need setting Multicast? Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY Serach NIC Get base IO address Get IRQ value ...

Page 57

... The descriptors that the AN983B supports to build in host memory are used as the pointers of these transmit and receive buffers. There are two structure types for the descriptor, Ring and Chain, supported by the AN983B and are shown as below. The type selection is controlled by the bit24 of RDES1 and the bit24 of TDES1. ...

Page 58

... AN983B Chain structure There is only one buffer per descriptor in chain structure. CSR3 or CSR4 Descriptor Pointer Fig - 6 Chain structure of frame buffer Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY Descriptor own Data Buffer --- Length 1 Buffer1 pointer Data Next point own Data Buffer ...

Page 59

... AN983B 8.2.2 THE POINT OF DESCRIPTOR MANAGEMENT OWN bit = 1, ready for network side access OWN bit = 0, ready for host side access Transmit Descriptor Pointers next packet to be transmitted own bit=2, packet1 and packet 2 are ready to transmit empty descriptor pointer end of ring Fig - 7 Transmit pointers for descriptor management Rev ...

Page 60

... AN983B Receive Descriptor Pointers own bit=1, next descriptor ready for incoming packet filled descriptor pointer end of ring Fig - 8 Receive pointers for descriptor management Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY Descriptor 0 Data Buffer Packet Packet 1 0 Packet 2 ADMtek Inc. ...

Page 61

... AN983B 8.3 TRANSMIT SCHEME AND TRANSMIT EARLY INTERRUPT 8.3.1 TRANSMIT FLOW The flow of packet transmit is shown as below. AN983B read descriptor available descriptor(own=1) read data and put into tx fifo no deferring and greater than tx threshold DO TRANSMIT read the rest data write descriptor generate interrupt 8.3.2 TRANSMIT PRE-FETCH DATA FLOW ...

Page 62

... PCI/miPCI Fast Ethernet Controller with integrated PHY transmit threshold IFG 1st packet check the next packet time handled by driver handled by driver ADMtek Inc. www.admtek.com.tw 2nd packet 1st packet is transmitted, check the 3rd packet handled by AN983B The saved time when transmit early interrupt is implemented handled by AN983B 62 ...

Page 63

... Fig - 12 Receive data flow (without early interrupt and with early interrupt) Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY handled by driver handled by AN983B ADMtek Inc. www.admtek.com.tw finish time finish time 63 ...

Page 64

... AN983B FIFO-to-host memory operation receive early interrupt driver read header(early) higher layer process(early) driver read the rest data tim e Fig - 13 Detailed receive early interrupt flow Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY The size of 1st descriptor is program ed as the header ...

Page 65

... Receive Data Decapsulation When operate in 100BASE-TX mode the AN983B detects a JK code for a preamble as well code for the packet end code is not detected, the AN983B will abort this frame receiving and wait for a new JK code detection code is not detected, the AN983B will report a CRC error ...

Page 66

... IFG1 time (64-bit time carrier is detected on the medium during this time, the AN983B will reset the IFG1 time counter and restart to monitor the channel for an idle again. 2. IFG2 time (32-bit time): After counting the IFG2 time the AN983B will access the channel even though a carrier has been sensed on the network ...

Page 67

... AN983B Start-of-Stream Delimiter-SSD (/J/K transmission stream, the first 16 nibbles are MAC preamble. In order to let partner delineate the boundary of a data transmission sequence and to authenticate carrier events, the transceiver will replace the first 2 nibbles of the MAC preamble with /J/K/ code-groups. End-of-Stream Delimiter-ESD (/T/R/) In order to indicate the termination of the normal data transmissions, the transceiver will insert 2 nibbles of /T/R/ code-group after the last nibble of FCS ...

Page 68

... AN983B cabling reliable adaptive equalizer and baseline wander to compensate all the amplitude attenuation and phase shifting are necessary. In the transceiver, it provides the robust circuits to perform these functions. MLT3 to NRZI Decoder and PLL for Data Recovery After receiving the proper MLT3 signals, the transceiver converts the MLT3 to NRZI code for further processing ...

Page 69

... AN983B NRZ to NRZI converter then loop-back to the receive path into the input of NRZI to NRZ converter. In the 10BASE-T loop-back operation, the data is through transmitting path and loop-back from the output of the Manchester encoder into the input of Phase Lock Loop circuit of receive path. ...

Page 70

... Receive Operation for PAUSE function Upon reception of a valid MAC Control frame, the AN983B will start a timer for the length of time specified by the MAC Control Parameters field. When the timer value reaches zero then the AN983B ends PAUSE state ...

Page 71

... AN983B the AN983B ends the PAUSE state immediately. Wait for Transmission Completed transmission_in_progress = false* DA=(01-80-C2-00-00-01 + Phys-address) PAUSE FUNCTION n_slots_rx=data[17:32] Start pause_timer(n_slots_rx*slot_time) UCT Fig - 15 PAUSE operation receive state diagram Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY Opcode = PAUSE Function DA = (01-80-C2-00-00-01 + Phys-address) END PAUSE ADMtek Inc ...

Page 72

... For ensuring proper reset operation, at least 100µs active Reset input signal is required. Second, software reset, when bit 0 of CSR0 register is set to 1, the AN983B will reset entire circuits and register to default value then clear the bit 0 of CSR0 to 0. ...

Page 73

... AN983B contains to default value then clear the bit 15 of PHY register 8.8 WAKE ON LAN FUNCTION The AN983B can assert a signal to wake up the system when it received a Magic Packet from the network. The Wake on LAN operation is described as follow. 8.8.1 THE MAGIC PACKET FORMAT Valid destination address that can pass the address filter of the AN983B The payload of frame must include at least 6 contiguous ‘ ...

Page 74

... POWER STATES DO (Fully On) In this state the AN983B operates as full functionality and consumes its normal power. While in the D0 state, if the PCI clock is lower than 16MHz, the AN983B may not receive or transmit frames properly this state the AN983B doesn’t response to any accesses, except configuration space and full function context in place ...

Page 75

... AN983B B2 maintained and Rx B0, B1, Configuration lost, full D3hot B2 initialization required upon return All configurations lost. D3cold Power-on defaults in place on return to D0 Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY Full speed access (B0, B1) Stopped to PCI configuration Full speed access (B0, B1) ...

Page 76

... PCI Subsystem Vendor ID MIN_GNT value. 0xFF 28 1 MAX_LAT value. 0xFF 29 4 CIS Pointer, it will be loaded into CR10. 0x0202 2A 2 CSR18 (CR) bit 31-16 recall data. Please reference AN983B Spec. 2E 0x22 Reserved, should be zero Cardbus CIS length. 52 0x2A Reserved, should be zero CheckSum, the least significant two bytes of FCS for data stored in offset 0.7D ...

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... AN983B 0xFFFF 0x0100 0x0200 0x0400 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0010 0x0013 0x0015 Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY Software Driver Default Auto-Negotiation Power-on Auto-detection Auto Sense 10BaseT BNC AUI 100BaseTx 100BaseT4 100BaseFx 10BaseT Full Duplex 100BaseTx Full Duplex 100BaseFx Full Duplex ADMtek Inc ...

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... AN983B 10. ELECTRICAL SPECIFICATIONS AND TIMINGS 10.1 ABSOLUTE MAXIMUM RATINGS Supply Voltage (Vcc) Input Voltage Output Voltage Storage Temperature Ambient Temperature ESD Protection 10.2 DC SPECIFICATIONS General DC Specifications Parameter Description Supply Voltage Vcc Power Supply Icc PCI Interface DC Specifications Parameter Description Input LOW Voltage Vilp ...

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... AN983B Input Pin Capacitance Cinf 10.3 AC SPECIFICATIONS PCI Signaling AC Specifications for 3.3V Parameter Description Switching Current High Ioh (AC) Switching Current Low Iol (AC) Slew Rate Unloaded Output Rise Time Tr Unloaded Output Fall Time Tf 10.4 TIMING SPECIFICATIONS PCI Clock Specifications Parameter Description Clock Cycle Time Tcyc ...

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... AN983B PCI Timings Parameter Description Access time – bused signals Tval Access time –point to point Tval (ptp) Float to Active Delay Ton Active to Float Delay Toff Input Set up Time to Clock – Tsu bused signals Input Set up Time to Clock - Tsu (ptp) point to point ...

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... AN983B CLK OUTPUT Delay Tri-state OUTPUT INPUT 1.5V Flash Interface Timings Parameter Description Read cycle time Trc Chip enable access time Tce Address access time Taa Output enable access time Toe #CE low to active output Tclz #OE low to active output Tolz #CE high to active output ...

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... AN983B #WE and #CE hold time Tch #OE high setup time Toes #OE high hold time Toeh #CE pulse width Tcp #WE pulse width Twp #WE high width Twph Data setup time Tds Data hold time Tdh Byte load cycle time Tblc Byte laod cycle time out Tblco ...

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... AN983B ADDRESS Trc CS# OE# DATA EEPROM Interface Timings (AC/AD) Parameter Description Serial Clock Frequency Tscf Delay from CS High to SK High 2.7V<Vcc<5.5V Tecss Delay from SK Low to CS Low 2.7V<Vcc<5.5V Tecsh Setup Time Tedts Hold Time of DI after SK Tedth CS Low Time Tecsl Rev ...

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... AN983B CS Tecss CLK Tedts DI Fig - 20 Serial EEPROM timing MII Interface Timing TX_CLK TXD<3:0>,TX_EN, TX_ER 0 ns Min 25 ns MAX Fig- 21 Transmit signal timing relationships at the MII Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY Tecsh Tedth ADMtek Inc. www.admtek.com.tw Tecsl V ih(min) ...

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... AN983B RX_CLK RXD<3:0>,RX_DV, RX_ER Fig- 22 Receive signal timing relations at the MII MDC MDIO 10 ns MIN Fig- Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY 10 ns MIN 23 MDIO sourced by STA ADMtek Inc. www.admtek.com.tw V ih(min) V il(max) V ih(min) V il(max MIN V ih(min) V il(max) ...

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... AN983B MDC MDIO 0 ns Min 300 ns MAX FIG- 24 MDIO SOURCED BY PHY Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY ADMtek Inc. www.admtek.com.tw V ih(min) V il(max) V ih(min) V il(max) 86 ...

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... AN983B 11. PACKAGE Fig - 25 Package outline for the AN983B / AN983BL Dimensions for 128 –pin PQFP Package (AN983B) Symbol Description Overall Height A Stand Off A1 Lead Width b Lead Thickness c Terminal Dimension 1 D Package Body 1 D1 Terminal Dimension 2 E Package Body 2 E1 Lead Pitch ...

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... AN983B Dimensions for 128 –pin LQFP Package (AN983BL) Symbol Description Overall Height A Stand Off A1 Lead Width b Lead Thickness c Terminal Dimension 1 D Package Body 1 D1 Terminal Dimension 2 E Package Body 2 E1 Lead Pitch e1 Foot Length L1 Lead Angle T Coplanarity Y Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY ...

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... AN983B 12. LAYOUT GUIDE (REV.1.0B) Layout Guide Revision History: Revision Date Revision 1.0b October, 2000 12.1 PLACEMENT Keep the distance as short as possible between Centaur-P and transformer, as well as transformer and RJ45. Make crystal device cross to Centaur-P pin x1 x2, and away from the following item: 1). Tx+/- Rx+/- differential pairs 2) ...

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... AN983B 6). Keep the distance between the Tx and Rx differential pairs large, even separate ground planes underneath Tx and Rx signal pairs. 7). Away from clock and power trace. 8). If possible, with GND plane around. 9 rout trace must cross, you can swap the trace between chip and transformer, and transformer to RJ45, too ...

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... The sample board Vcc and GND plane at below side. RJ45 Transformer Chassis System Ground Ground Rev. 1.8 PCI/miPCI Fast Ethernet Controller with integrated PHY Power Switch Power PLANE AN983B VCC FROM PCI Good VCC PLANE UNDER CHIP ADMtek Inc. www.admtek.com.tw Power Switch 91 ...

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