AT45DB ATMEL Corporation, AT45DB Datasheet
AT45DB
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AT45DB Summary of contents
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... The AT45DB011 is a 2.7-volt only, serial interface Flash memory suitable for in-sys- tem reprogramming. Its 1,081,344 bits of memory are organized as 512 pages of 264 bytes each. In addition to the main memory, the AT45DB011 also contains one SRAM data buffer of 264 bytes. Unlike conventional Flash memories that are accessed ran- domly with multiple address lines and a parallel interface, the DataFlash uses a serial interface to sequentially access its data ...
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... AT45DB011 2 To allow for simple in-system reprogrammability, the AT45DB011 does not require high input voltages for pro- gramming. The device operates from a single power sup operations. The AT45DB011 is enabled through the chip ...
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... To start a page read, the 8-bit opcode, 52H, is followed by 24 address bits and 32 don’t care bits. In the AT45DB011, the first six address bits are reserved for larger density devices (see Notes on page 9), the next nine address bits (PA8- ...
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... CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both the erase and the programming of the AT45DB011 4 page are internally self timed and should take place in a maximum time of t ...
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... When there is a low to high transition on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both the erase and ...
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... The device density is indicated using bits 5, 4, and 3 of the status register. For the AT45DB011, the three bits are 0, 0, and 1. The decimal value of these three binary bits does not equate to the device density; the three bits represent a ...
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DC Characteristics Symbol Parameter I Standby Current SB Active Current, Read I CC1 Operation Active Current, Program/Erase I CC2 Operation I Input Load Current LI I Output Leakage Current LO V Input Low Voltage IL V Input High Voltage IH ...
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... Waveform 2 – Inactive Clock Polarity High CS tCSS SCK HIGH AT45DB011 8 times for the SI signal are referenced to the low-to-high transition on the SCK signal. Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows timing that is compatible with SPI Mode 3. ...
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Reset Timing (Inactive Clock Polarity Low Shown) CS SCK RESET HIGH IMPEDANCE SO SI Command Sequence for Read/Write Operations (Except Status Register Read) SI MSB larger densities Notes: 1. “r” designates bits reserved for larger densities recommended ...
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... CMD Buffer Write CS SI CMD Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page Each transition represents 8 bits and 8 clock cycles AT45DB011 10 FLASH MEMORY ARRAY BUFFER TO MAIN MEMORY PAGE PROGRAM BUFFER (264 BYTES) BUFFER WRITE I/O INTERFACE SI PA6-0, BFA8 ...
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... The following block diagram and waveforms illustrate the various read sequences available. PAGE (264 BYTES) Main Memory Page Read CS SI CMD r ···r , PA8-7 SO Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer Buffer Read ...
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... COMMAND OPCODE Buffer Read CS SCK 1 2 tSU COMMAND OPCODE Status Register Read CS SCK 1 2 tSU HIGH-IMPEDANCE SO AT45DB011 HIGH-IMPEDANCE HIGH-IMPEDANCE COMMAND OPCODE ...
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... Detailed Bit-Level Read Timing – Inactive Clock Polarity High Main Memory Page Read CS SCK 1 2 tSU COMMAND OPCODE Buffer Read CS SCK 1 2 tSU COMMAND OPCODE Status Register Read CS SCK tSU HIGH-IMPEDANCE ...
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... PA4 PA3 PA2 PA1 PA0 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 • • • X (64th bit) AT45DB011 14 Table 1 Main Memory Page to Buffer Transfer Opcode 54H 53H ...
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... PA4 PA3 PA3 PA2 PA2 PA1 PA1 PA0 PA0 Table 2 Main Memory Page Block Page Program Erase Erase Through Buffer Opcode 81H 50H ...
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... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. AT45DB011 16 START provide address and data ...
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... Figure 2. Algorithm for Randomly Modifying Data MAIN MEMORY PAGE PROGRAM Notes preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations within that sector Page Address Pointer must be maintained to indi- cate which page rewritten ...
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... Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 14X 14-Lead, 0.170" Wide, Plastic Thin Shrink Small Outline Package (TSSOP) AT45DB011 18 Ordering Code 0.01 AT45DB011-JC AT45DB011-SC AT45DB011-XC 0.01 AT45DB011-JI AT45DB011-SI AT45DB011-XI Package Type Package Operation Range 32J Commercial 8S2 ( 14X 32J Industrial ...
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Packaging Information 32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-016 AE .045(1.14) X 45° PIN NO. 1 IDENTIFY .553(14.0) .547(13.9) .032(.813) .595(15.1) .026(.660) .585(14.9) .050(1.27) TYP .300(7.62) REF .430(10.9) .390(9.90) AT CONTACT POINTS ...