BS62LV1027 BSI [Brilliance Semiconductor], BS62LV1027 Datasheet

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BS62LV1027

Manufacturer Part Number
BS62LV1027
Description
Very Low Power/Voltage CMOS SRAM
Manufacturer
BSI [Brilliance Semiconductor]
Datasheet

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R0201-BS62LV1027
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
• High speed access time :
• Automatic power down when chip is deselected
FEATURES
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor, Inc
BS62LV1027SC
BS62LV1027TC
BS62LV1027STC
BS62LV1027PC
BS62LV1027JC
BS62LV1027DC
BS62LV1027SI
BS62LV1027TI
BS62LV1027STI
BS62LV1027PI
BS62LV1027JI
BS62LV1027DI
Vcc = 3.0V
Vcc = 5.0V
-55
-70
PRODUCT
FAMILY
BSI
VCC
CE2
A11
A13
A15
A16
A14
A12
WE
NC
A9
A8
A7
A6
A5
A4
55ns
70ns
GND
DQ0
DQ1
DQ2
A16
A14
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A7
A6
A5
A4
A3
A2
A1
A0
C-grade : 14mA (@70ns) operating current
C-grade : 38mA (70ns) operating current
C-grade : 17mA (@55ns) operating current
C-grade : 46mA (55ns) operating current
I- grade : 18mA (@55ns) operating current
I- grade : 15mA (@70ns) operating current
0.1uA (Typ.) CMOS standby current
I- grade : 47mA (55ns) operating current
I- grade : 39mA (70ns) operating current
0.6uA (Typ.) CMOS standby current
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV1027SC
BS62LV1027SI
BS62LV1027PC
BS62LV1027PI
BS62LV1027JC
BS62LV1027JI
TEMPERATURE
-40
BS62LV1027TC
BS62LV1027STC
BS62LV1027TI
BS62LV1027STI
+0
OPERATING
O
O
C to +70
C to +85
Very Low Power/Voltage CMOS SRAM
128K X 8 bit
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
O
O
C
C
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
. reserves the right to modify document contents without notice.
2.4V ~ 5.5V
2.4V ~ 5.5V
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
RANGE
Vcc
55ns : 3.0~5.5V
70ns : 2.7~5.5V
SPEED
55/70
55/70
(ns)
• Easy expansion with CE2, CE1, and OE options
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
The BS62LV1027 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA at 3V/25
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV1027 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1027 is available in DICE form , JEDEC standard 32 pin
mm STSOP and 8mmx20mm TSOP.
450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP,8mm x13.4
1
DESCRIPTION
BLOCK DIAGRAM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A12
A14
A16
A15
A13
CE2
CE1
Vdd
Gnd
A11
WE
OE
A6
A7
A8
A9
Vcc=5.0V Vcc=3.0V
8.0uA
20uA
Address
STANDBY
(I
Buffer
CCSB1
Input
o
C and maximum access time of 55ns at 3V/85
8
Control
POWER DISSIPATION
8
, Max)
1.3uA
2.5uA
20
Output
Buffer
Buffer
Data
Input
Data
Decoder
Row
Vcc=3V
15mA
14mA
70ns
Operating
(I
CC
8
, Max)
1024
8
Vcc=5V
38mA
39mA
BS62LV1027
70ns
A5
Address Input Buffer
A4
Column Decoder
Memory Array
Sense Amp
Write Driver
1024 x 1024
Column I/O
A3 A2 A1 A0 A10
SOP-32
TSOP-32
STSOP-32
PDIP-32
SOJ-32
DICE
SOP-32
TSOP-32
STSOP-32
PDIP-32
SOJ-32
DICE
PKG TYPE
1024
128
14
Revision 2.1
Jan.
o
C.
2004

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BS62LV1027 Summary of contents

Page 1

... The BS62LV1027 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV1027 is available in DICE form , JEDEC standard 32 pin 450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP,8mm x13.4 mm STSOP and 8mmx20mm TSOP. ...

Page 2

... RANGE -0 Vcc+0.5 Commercial O -40 to +85 C Industrial O -60 to +150 C 1.0 W CAPACITANCE 20 mA SYMBOL This parameter is guaranteed and not 100% tested. 2 BS62LV1027 Function I/O OPERATION Vcc CURRENT High CCSB High OUT AMBIENT TEMPERATURE + ...

Page 3

... IN IN See Retention Waveform ( CE1 Controlled ) Data Retention Mode ≥ V 1.5V DR Vcc t CDR ≥ CE1 Vcc - 0. CE2 Controlled ) Data Retention Mode V ≧ 1.5V DR Vcc t CDR CE2 ≦ 0. BS62LV1027 (1) MIN. TYP. MAX. Vcc=3.0V -0.5 -- 0.8 Vcc=5.0V 2.0 Vcc=3.0V -- Vcc+0.3 2.2 Vcc=5. Vcc=3. 0.4 Vcc=5.0V Vcc=3.0V 2 Vcc=5 ...

Page 4

... R0201-BS62LV1027 WAVEFORM = 30pF+1TTL L = 100pF+1TTL - DESCRIPTION (CE1) (CE2) (CE1) (CE2) (CE1) (CE2) 4 BS62LV1027 KEY TO SWITCHING WAVEFORMS INPUTS OUTPUTS MUST BE MUST BE STEADY STEADY MAY CHANGE WILL BE FROM CHANGE FROM MAY CHANGE WILL BE FROM CHANGE FROM ...

Page 5

... The parameter is guaranteed but not 100% tested. R0201-BS62LV1027 ACS1 t ACS2 (5) t CLZ OLZ t ACS1 (5) t CLZ1 t ACS2 (5) t CLZ2 and CE2 IH. 5 BS62LV1027 CHZ1, CHZ2 t OH (5) t OHZ (1,5) t CHZ1 (2,5) t CHZ2 Revision 2.1 Jan. 2004 ...

Page 6

... Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (5) ( (4,10) t OHZ 6 BS62LV1027 CYCLE TIME : 70ns CYCLE TIME : 55ns (Vcc = 2.7~5.5V) (Vcc = 3.0~5.5V) MIN. TYP. MAX. MIN. TYP. MAX ...

Page 7

... The parameter is guaranteed but not 100% tested. 11 measured from the later of CE1 going low or CE2 going high to the end of write. CW R0201-BS62LV1027 t WC (11 (5) (5) (11 ( (4,10) t WHZ ). IL 7 BS62LV1027 t WR2 ( (7) ( (8,9) DH Revision 2.1 Jan. 2004 ...

Page 8

... BSI ORDERING INFORMATION BS62LV1027 X X Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments ...

Page 9

... BSI PACKAGE DIMENSIONS (continued) STSOP - 32 TSOP - 32 R0201-BS62LV1027 BS62LV1027 9 Revision 2.1 Jan. 2004 ...

Page 10

... BSI PACKAGE DIMENSIONS (continued) PDIP - 32 SOJ - 32 R0201-BS62LV1027 10 BS62LV1027 Revision 2.1 Jan. 2004 ...

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