CA91C142-33CE Tundra Semiconductor, CA91C142-33CE Datasheet
CA91C142-33CE
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CA91C142-33CE Summary of contents
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Universe II™ User Manual Spring 1998 http://www.tundra.com ...
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... Universe II™ User Manual Copyright 1998, Tundra Semiconductor Corporation All rights reserved. Document: 8091142.MD300.01 Printed in Canada Tundra and Tundra logo are registered trademarks of Tundra Semiconductor Corporation. Universe II, Universe, SCV64, Trooper II and QSpan are trademarks of Tundra Semiconductor Corporation. BI-Mode registered trademark of DY-4 Systems, Inc. ...
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Overview Chapter 1 Introduction Chapter 2 Functional Description Chapter 3 Description of Signals Chapter 4 Signals and DC Characteristics Appendix A Registers Appendix B Performance Appendix C Typical Applications Appendix D Reliability Prediction Appendix E Cycle Mapping Appendix F Operating ...
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iv ...
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Table of Contents 1 Introduction .......................................................................................................... 1-1 1.1 Features ................................................................................................... 1-1 1.2 Benefits of the Universe II ...................................................................... 1-2 1.3 Past and Future of the Universe .............................................................. 1-3 1.4 About This Document............................................................................. 1-4 1.5 Universe II Technical Support ................................................................ 1-5 ...
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Universe II as VMEbus Master.............................................. 2-9 2.2.2.1 Addressing Capabilities .................................................. 2-9 2.2.2.2 Data Transfer Capabilities ............................................ 2-10 2.2.2.3 Cycle Terminations....................................................... 2-13 2.2.3 Universe as VMEbus Slave.................................................. 2-13 2.2.3.1 Coupled Transfers......................................................... 2-14 2.2.3.2 Posted Writes ................................................................ 2-15 2.2.3.3 Prefetched Block ...
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Termination Phase ........................................................ 2-33 2.3.1.6 Parity Checking............................................................. 2-34 2.3.2 Universe II as PCI Master .................................................... 2-35 2.3.2.1 PCI Burst Transfers ...................................................... 2-36 2.3.2.2 Termination................................................................... 2-37 2.3.2.3 Parity ............................................................................. 2-37 2.3.3 Universe II as PCI Target..................................................... 2-38 2.3.3.1 Overview....................................................................... 2-38 ...
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Interrupt Generation .............................................................................. 2-62 2.6.1 PCI Interrupt Generation...................................................... 2-63 2.6.2 VMEbus Interrupt Generation.............................................. 2-65 2.7 Interrupt Handling................................................................................. 2-68 2.7.1 PCI Interrupt Handling......................................................... 2-68 2.7.2 VMEbus Interrupt Handling................................................. 2-68 2.7.2.1 Bus Error During VMEbus IACK Cycle ...................... 2-70 2.7.3 Internal ...
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Registers.............................................................................................. 2-100 2.9.1 2.9.2 2.9.2.1 2.9.2.2 2.9.2.3 2.9.3 2.9.3.1 2.9.3.2 2.9.3.3 2.9.4 2.9.5 2.10 Utility Functions ................................................................................. 2-110 2.10.1 2.10.1.1 2.10.1.2 2.10.1.3 2.10.2 2.10.2.1 2.10.2.2 2.10.3 2.10.4 2.10.4.1 2.10.4.2 2.10.5 3 Description of Signals .......................................................................................... ...
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PCI Bus Signals ..................................................................................... 3-5 4 Signals and DC Characteristics .......................................................................... 4-1 4.1 Terminology............................................................................................ 4-1 4.2 DC Characteristics and Pin Assignments................................................ 4-2 Appendix A – Registers .............................................................................................App A-1 Appendix B – Performance ....................................................................................... App B-1 B.1 PCI Slave Channel ...
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Appendix C – Typical Applications ......................................................................... App C-1 C.1 VME Interface................................................................................. App C-1 C.1.1 C.1.1.1 C.1.2 C.1.3 C.2 PCI Bus Interface ............................................................................ App C-7 C.2.1 C.2.2 C.3 Manufacturing Test Pins ............................................................... App C-10 C.4 Decoupling VDD and VSS on the ...
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xii ...
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List of Figures Figure 2.1 : Architectural Diagram for the Universe II ............................................ 2-3 Figure 2.2 : Influence of Transaction Data Width and Target Image Data Width on Data Packing/Unpacking ............................................ 2-12 Figure 2.3 : VMEbus Slave Channel Dataflow....................................................... 2-14 ...
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Figure B.4 : Several Non-Block Decoupled Writes - Universe II as VME Master ............................................................................................ App B-6 Figure B.5 : BLT Decoupled Write - Universe II as VME Master ................... App B-6 Figure B.6 : Coupled Read Cycle - Universe II ...
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List of Tables Table 1.1 : Suffixes for Active Low Signals ........................................................... 1-6 Table 2.2 : PCI Address Line Asserted as a Function of VA[15:11] .................... 2-21 Table 2.3 : Command Type Encoding for Transfer Type ..................................... 2-32 Table 2.4 ...
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Table 4.3 : PCI Bus Address/Data Pins ................................................................... 4-7 Table 4.4 : VMEbus Address Pins........................................................................... 4-9 Table 4.5 : VMEbus Data Pins .............................................................................. 4-10 Table 4.6 : Pin Assignments for Power and Ground ............................................. 4-11 Table 4.7 : Pinout for ...
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Table A.25 : Special Cycle Control Register (SCYC_CTL)........................... App A-31 Table A.26 : Special Cycle PCI Bus Address Register (SCYC_ADDR)........ App A-32 Table A.27 : Special Cycle Swap/Compare Enable Register (SCYC_EN) .... App A-33 Table A.28 : Special Cycle Compare ...
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Table A.56 : DMA Linked List Update Enable Register (D_LLUE) ............. App A-64 Table A.57 : PCI Interrupt Enable Register (LINT_EN) ................................ App A-65 Table A.58 : PCI Interrupt Status Register (LINT_STAT) ............................. App A-67 Table A.59 : PCI Interrupt ...
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Table A.89 : VMEbus Slave Image 1 Control (VSI1_CTL)......................... App A-103 Table A.90 : VMEbus Slave Image 1 Base Address Register (VSI1_BS).... App A-104 Table A.91 : VMEbus Slave Image 1 Bound Address Register (VSI1_BD) App A-105 Table A.92 : ...
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Table A.119 : VMEbus Slave Image 6 Bound Address Register (VSI6_BD) App A-133 Table A.120 : VMEbus Slave Image 6 Translation Offset (VSI6_TO) .......... App A-134 Table A.121 : VMEbus Slave Image 7 Control (VSI7_CTL)......................... App A-135 Table A.122 : ...
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... VMEbus Interface Components—Universe II User Manual 1 Introduction 1.1 Features The Universe II (CA91C142) is the de facto industry standard PCI bus to VMEbus bridge, providing: • 64-bit, 33 MHz PCI bus interface, • fully compliant, high performance 64-bit VMEbus interface, • integral FIFOs buffer multiple transactions in both directions, • ...
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... The elegant design of the Tundra Universe II, some of the best applications engineers in the industry, and this manual will make it as easy as possible for you to use the most sophisticated VMEbus interface. 1-2 Universe II User Manual Tundra Semiconductor Corporation ...
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... Universe II User Manual 1.3 Past and Future of the Universe The Universe II (CA91C142 pin- and software-compatible revision of the Universe (CA91C042). The Universe was developed subsequently to the SCV64, Tundra’s VME interface for non-PCI applications. The Universe II is the next generation of the Universe, and has been designed to exceed new customer expectations and to correct errata in the original Universe ...
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... Chapters 3 and 4. The Appendices are reference sources necessary for the implementation of the Universe II. In addition, the Appendices contain application information to aid the user in system design. The Index provides a means to quickly access information on a keyword basis. 1-4 Universe II User Manual Tundra Semiconductor Corporation ...
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... The Designer’s Resource Center. You can tailor how the Tundra web site is presented to you by using this web resource, available from http://www.tundra.com. There, you may also register to receive automatic e- Tundra Semiconductor Corporation Universe II Technical Support 1-5 ...
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... Caution: This symbol alerts the reader to procedures or operating levels which ! may result in misuse of or damage to the Universe II. Note: This symbol directs the reader’s attention to useful information or suggestions. 1-6 Used for active low signals on PCI, and Tundra Semiconductor Corporation Universe II User Manual Example RST# VRSYSRST# SYSRESET* ...
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... Interface” or “Slave Interface” is used to denote the Universe II as target (or slave) of the bus. For example if the Universe II accesses a memory chip on the PCI bus, we might write: “The PCI Master Interface writes to the external PCI target.” Tundra Semiconductor Corporation Conventions 1-7 ...
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... Conventions 1-8 Universe II User Manual Tundra Semiconductor Corporation ...
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... Section 2.8, “DMA Controller”, on page 2-77 describes the operation of the Universe II’s Direct Memory Access Controller, • Section 2.9, “Registers”, on page 2-100 gives an overview of the Universe II’s registers and how they can be accessed, • Section 2.10, “Utility Functions”, on page 2-110 describes resets, power-up options, test modes, and clocks. Tundra Semiconductor Corporation 2-1 ...
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... With a coupled cycle, the VMEbus master only receives data acknowledgment when the transaction is complete on the PCI bus. This means that the VMEbus is unavailable to other masters while the PCI bus transaction is executed. 2-2 Universe II User Manual Tundra Semiconductor Corporation ...
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... Interrupt Channel always has priority over the other two channels. Several mechanisms are available to configure the relative priority that the PCI Bus Target Channel and DMA Channel have over ownership of the VMEbus Master Interface. Tundra Semiconductor Corporation DMA Channel VMEbus DMA bidirectional FIFO ...
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... PCI bus or VMEbus interrupt output pins. Interrupt sources mapped to VMEbus interrupts are generated on the VMEbus interrupt output pins VIRQ# [7:1]. When a software and hardware source are assigned to the same VIRQn# pin, the software source always has higher priority. 2-4 Universe II User Manual Tundra Semiconductor Corporation ...
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... The DMA controller can be programmed to perform multiple blocks of transfers using entries in a linked-list. The DMA will work through the transfers in the linked-list following pointers at the end of each linked-list entry. Linked-list operation is initiated through a pointer in an internal Universe II register, but the linked-list itself resides in PCI bus memory. Tundra Semiconductor Corporation Architectural Overview 2-5 ...
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... STATUS/ID. The PCI Target Channel requests the VMEbus Master Interface to service the following conditions: • the TXFIFO contains a complete transaction, or • if there is a coupled cycle request. 2-6 Universe II User Manual Tundra Semiconductor Corporation ...
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... BRn* line. By requesting the bus frequently, requesters far down the daisy chain may be prevented from ever obtaining bus ownership. This is referred to as “starving” those requesters. Note that in order to achieve fairness, all bus requesters in a VMEbus system must be set to Fair mode. Tundra Semiconductor Corporation VMEbus Interface 2-7 ...
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... VOWN bit is cleared (in other words, if the VMEbus is acquired through the use of the VOWN bit, the Universe II does not release BBSY* until the VOWN bit is cleared—see “VME Lock Cycles—Exclusive Access to VMEbus Resources” on page 2-47). 1. This setting is overridden if the VOWN mechanism is used. 2-8 Universe II User Manual 1 , Tundra Semiconductor Corporation ...
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... MBLT cycles, where the VMEbus specification does not permit it. The address and AM codes that are generated by the Universe II are functions of the PCI address and PCI target image programming (see “PCI Bus Target Images” on page 2-53) or through DMA programming. Tundra Semiconductor Corporation VMEbus Interface 2-9 ...
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... PCI data beat the above example the PCI target image has a VDW set to 8 bits, then the three-byte PCI data beat will be broken into three single-byte VMEbus cycles. 2-10 Universe II User Manual Tundra Semiconductor Corporation ...
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... During DMA operations, the Universe II will attempt block transfers to the maximum length permitted by the VMEbus specification (256 bytes for BLT, 2 Kbytes for MBLT) and as limited by the VON counter (see “DMA VMEbus Ownership” on page 2-81). Tundra Semiconductor Corporation VMEbus Interface 2-11 ...
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... The Universe II provides indivisible transactions with the VMEbus lock commands and the VMEbus ownership bit (see “VME Lock Cycles—Exclusive Access to VMEbus Resources” on page 2-47). 2-12 Universe II User Manual Data width of PCI transaction Maximum data width programmed into PCI target image WRITE (UNPACKING) READ (PACKING) Tundra Semiconductor Corporation VMEBUS SIDE ...
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... VMEbus master (note that the Universe II cannot reflect a cycle on the VMEbus and access itself). Depending upon the programming of the slave image, different possible transaction types result (see “VME Slave Images” on page 2-50 for a description of the types of accesses to which the Universe II responds). Tundra Semiconductor Corporation VMEbus Interface 2-13 ...
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... The only exception to this is when a D64 VMEbus transaction is mapped to D32 on the PCI bus. The data width of the PCI bus depends on the 2-14 Universe II User Manual PREFETCHED READ DATA RDFIFO COUPLED READ DATA RXFIFO Tundra Semiconductor Corporation VMEbus SLAVE INTERFACE ...
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... RXFIFO. The final two data phases (32 bits combined) are queued in the next RXFIFO entry. When you add the address entry to the three data entries, this VMEbus block write has been stored in a total of four RXFIFO entries. Tundra Semiconductor Corporation VMEbus Interface 2-15 ...
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... Prefetching of read data occurs for VMEbus block transfers (BLT, MBLT) in those slave images that have the prefetch enable (PREN) bit set (see “VME Slave Images” on page 2-50). In the VMEbus Slave Channel, prefetching is not supported for non BLT/MBLT transfers. 2-16 Universe II User Manual Tundra Semiconductor Corporation ...
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... RDFIFO for another PCI burst read transaction is determined by the setting of the PCI aligned burst size (PABS in the MAST_CTL register, Table A.81). If PABS is set for 32 bytes, there must be four entries available in the RDFIFO; for aligned burst size set to 64 bytes, eight Tundra Semiconductor Corporation VMEbus Interface 2-17 ...
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... PCI bus, the Universe II will relinquish its ownership of LOCK# in accord with the PCI bus Specification the responsibility of the user to verify the R_MA and R_TA status bits of the PCI_CSR status register to determine whether or not ownership of LOCK# was lost. 2-18 Universe II User Manual Tundra Semiconductor Corporation ...
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... Location Monitors Universe II has four location monitors to support a VMEbus broadcast capability. The location monitors’ image is a 4-Kbyte image in A16, A24 or A32 space on the VMEbus. If enabled, an access to a location monitor causes the PCI Master Interface to generate an interrupt. Tundra Semiconductor Corporation VMEbus Interface 2-19 ...
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... Number field (BUS_NO[7:0] in Table A.81). If the bits are the same as the BUS_NO field, then a TYPE 0 access is generated. If they are not the same, a Type 1 configuration access is generated. The PCI bus-generated address then becomes an unsigned addition of the incoming VMEbus address and the VMEbus slave image translation offset. 2-20 Universe II User Manual Tundra Semiconductor Corporation ...
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... Other address bits are irrelevant—they are not mapped to the PCI bus. Table 2.2 : PCI Address Line Asserted as a Function of VA[15:11] a VA[15:11] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 Tundra Semiconductor Corporation b PCI Address Line Asserted VMEbus Interface ...
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... VMEbus Address[15:11] identifies the PCI Device Number, • VMEbus Address[23:16] does not match the BUS_NO in MAST_CTL register, and • VMEbus Address[31:24] are mapped directly through to the PCI bus. 2-22 b PCI Address Line Asserted Tundra Semiconductor Corporation Universe II User Manual ...
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... VRAI_BS and VRAI_CTL (Table A.103) registers with information specifying the UCSR slave image (see “Power-Up Options” on page 2-115). Register access at power-up would be used in systems where the Universe II’s card has no CPU, or where register access for that card needs to be independent of the local CPU. Tundra Semiconductor Corporation VMEbus Interface 2-23 ...
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... AUTOID bit in the MISC_CTL register (Table A.82). This asserts IRQ2* and releases SYSFAIL*. After SYSFAIL* is released and the Universe II detects a level 2 IACK cycle, it responds with the STATUS/ID stored in its level 2 STATID register (which defaults to 0xFE). 2-24 Universe II User Manual Tundra Semiconductor Corporation ...
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... IACKIN*, then count four more clocks and assert IACKOUT* to the next board. Finally, the last board asserts IACKOUT* and the bus pauses until the data transfer time-out circuit ends the bus cycle by asserting BERR*. Tundra Semiconductor Corporation VMEbus Interface 2-25 ...
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... System Clock Driver The Universe II provides a 16 MHz SYSCLK signal derived from CLK64 when configured as SYSCON. 2- Figure 2.4 : Timing for Auto-ID Cycle Universe II User Manual Tundra Semiconductor Corporation ...
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... IACK Daisy-Chain Driver Module The IACK Daisy-Chain Driver module is enabled when the Universe II becomes system controller. This module guarantees that IACKIN* will stay high for at least specified in rule 40 of the VME64 specification. Tundra Semiconductor Corporation VMEbus Interface 2-27 ...
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... The Universe II will not respond to any interrupt it had outstanding. All VMEbus outputs from the Universe II will be tri-stated, so that the Universe II will not be driving any VMEbus signals. The only exception to this is the IACK and BG daisy chains which must remain in operation as before. 2-28 Universe II User Manual Tundra Semiconductor Corporation ...
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... BI bit in the MISC_CTL register, which will be effective only if the source of the BI-Mode is no longer active. That is, if VRIRQ# [1] is still being asserted while the ENGBI bit in the MISC_CTL register is set, then attempting to clear the BI bit in the MISC_CTL register will not be effective. Tundra Semiconductor Corporation VMEbus Interface 2-29 ...
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... Versus 64-Bit PCI The Universe II is configured with a 32-bit or 64-bit PCI data bus at power-up (see “PCI Bus Width” on page 2-119 for directions on how to configure the PCI bus width.) 2-30 Universe II User Manual Tundra Semiconductor Corporation ...
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... VMEbus Slave” on page 2-13). The command signals (on the C/BE# lines) contain information about Memory space, cycle type and whether the transaction is read or write. Table 2.3 below gives PCI the command type encoding implemented with the Universe II. Tundra Semiconductor Corporation PCI Bus Interface 2-31 ...
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... Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write and Invalidate Universe II User Manual Universe II Capability N/A N/A Target/Master Target/Master N/A N/A Target/Master Target/Master N/A N/A Target/Master Target/Master (See Text) N/A (See Text) (See Text) Tundra Semiconductor Corporation ...
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... STOP transaction which it will never be able to respond to, or during which a fatal error occurred. Although there may be a fatal error for the initiating application, the transaction completes gracefully, ensuring normal PCI operation for other PCI resources. Tundra Semiconductor Corporation PCI Bus Interface 2-33 ...
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... SERR# signal and setting a status bit in its registers. No interrupt is generated, and regardless of whether assertion of SERR# is enabled, the Universe II does not respond to the errored access. If powered 64-bit PCI environment, the Universe II uses PAR64 in the same way as PAR, except for AD[63:32] and C/BE[7:4]. 2-34 Universe II User Manual Tundra Semiconductor Corporation ...
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... PCI bus. As discussed elsewhere (“Universe as VMEbus Slave” on page 2-13), access from the VMEbus may be either coupled or decoupled. For a full description of the operation of these data paths, see “Universe as VMEbus Slave” on page 2-13. Tundra Semiconductor Corporation PCI Bus Interface 2-35 ...
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... RXFIFO empties), • filling the RDFIFO (receives a block read request from a VMEbus master to an appropriately programmed VMEbus slave image), or • performing DMA transfers All other accesses are treated as single data beat transactions on the PCI bus. 2-36 Universe II User Manual Tundra Semiconductor Corporation ...
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... In both address and data phases, the PAR signal provides even parity for C/BE#[3:0] and AD[31:0]. If the Universe II is powered 64-bit PCI environment, then PAR64 provides even parity for C/BE#[7:4] and AD[63:32]. Tundra Semiconductor Corporation PCI Bus Interface 2-37 ...
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... VMEbus. When one of its PCI target images is accessed, the Universe II responds with DEVSEL# within two clocks of FRAME# (making the Universe II a medium speed device, as reflected by the DEVSEL field in the PCI_CS register). 2-38 Universe II User Manual Tundra Semiconductor Corporation ...
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... VMEbus Slave” on page 2-13). Write transactions can be coupled or posted (see Figure 2.5 below and “PCI Bus Target Images” on page 2-53). To ensure sequential consistency, coupled operations (reads or writes) are only processed once all previously posted write operations have completed (i.e. the TXFIFO is empty). Tundra Semiconductor Corporation PCI Bus Interface 2-39 ...
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... PCI data beat the above example the PCI target image has a VDW set to 8 bits, then the three-byte PCI data beat will be broken into three single-byte VMEbus cycles. 2-40 Universe II User Manual POSTED WRITE DATA TXFIFO COUPLED WRITE DATA Tundra Semiconductor Corporation VMEbus MASTER INTERFACE ...
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... PCI target image Data width fits with maximum data width of the PCI target image PCI BUS SIDE Figure 2.6 : Influence of Transaction Data Width and Target Image Data Tundra Semiconductor Corporation Data width of PCI transaction WRITE (UNPACKING) READ (PACKING) Width on Data Packing/Unpacking PCI Bus Interface ...
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... Data-Transfer Phase”. No addresss matching is performed to verify whether the current coupled cycle matches the initiating coupled cycle external PCI Master requests a PCI I/O or RMW transfer with an illegal byte lane combination, the Universe II will exit the “Coupled Request Phase.” 2-42 Universe II User Manual Tundra Semiconductor Corporation ...
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... Since the Universe II cannot guarantee that data acknowledgment will be received from the VMEbus in time to meet these PCI latency requirements, the Uni- verse II performs a target-disconnect after the first data beat of every coupled write transaction. Tundra Semiconductor Corporation 1 the master, and then performs the transaction on the ...
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... VMEbus attributes in the PCI target image (see “PCI Bus Target Images” on page 2-53). For example, if the VMEbus data width is programmed to 16 bits, and block transfers are disabled, then each data entry in the TXFIFO corresponds to four transactions on the VMEbus. 2-44 Universe II User Manual Tundra Semiconductor Corporation ...
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... SCYC[1:0] in Table A.25 32-bit enable EN [31:0] in Table A.27 32-bit compare CMP [31:0] in Table A.28 32-bit swap SWP [31:0] in Table A.29 Tundra Semiconductor Corporation PCI Bus Interface Description specifies PCI bus target image address specifies whether the address specified in the ADDR field lies in PCI memory or I/O space disabled, RMW or ADOH ...
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... In the event that the Special Cycle Generator is accessed with a read cycle that does not meet the three criteria described above, the Universe II generates a Target-Abort. Thus it is the user’s responsibility to ensure that the Universe II is correctly programmed and accessed with correct byte-lane information. 2-46 Universe II User Manual Tundra Semiconductor Corporation ...
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... In the event that BERR* is asserted on the VMEbus once the Universe II has locked and owns the VMEbus the responsibility of the user to release ownership of the VMEbus by programming the VOWN bit in the MAST_CTL register to a value of 0. Tundra Semiconductor Corporation PCI Bus Interface 2-47 ...
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... VMEbus ownership bit will hold the bus until the exclusive access is no longer required. Alternatively, if the VMEbus Master Interface is programmed for ROR, the VMEbus ownership bit will ensure VMEbus tenure even if other VMEbus requesters require the VMEbus. 2-48 Universe II User Manual Tundra Semiconductor Corporation ...
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... The address of the errored transaction is latched in the VAERR register (Table A.108). When the Universe II receives a VMEbus error during a posted write, it generates an interrupt on the VMEbus and/or PCI bus depending upon whether the VERR and VERR interrupts are enabled (see “Interrupt Handling” on page 2-68). Tundra Semiconductor Corporation PCI Bus Interface 2-49 ...
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... Description maximum of 4 GBytes) A16, A24, A32, User 1, User 2 supervisor and/or non-privileged program and/or data Description address Memory, I/O, Configuration RMW enable bit Description enable bit posted write enable bit prefetched read enable bit enables 64-bit PCI bus transactions Tundra Semiconductor Corporation ...
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... LLRMW bit is set, single cycle reads will always be mapped to single data beat locked PCI transactions. Setting this bit has no effect on non-block writes: they can be coupled or decoupled. However, note that only accesses to PCI Memory Space are decoupled, accesses to I/O or Configuration Space are always coupled. Tundra Semiconductor Corporation Slave Image Programming 2-51 ...
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... PCI bus then performance can be improved by disabling LD64EN on the VMEbus slave images. In order for a VMEbus slave image to respond to an incoming cycle, the PCI Master Interface must be enabled (bit BM in the PCI_CSR register, Table A.3). 2-52 A32 Image VME [31..12] VME [11..0] PCI [31..12] PCI [11..0] Tundra Semiconductor Corporation Universe II User Manual ...
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... TXFE status bit in the MISC_STAT register (Table A.83) or perform a read from that image. If the programming for an image is changed after the transaction is queued in the FIFO, the transaction’s attributes are not changed. Only subsequent transactions are affected by the change in attributes. Tundra Semiconductor Corporation Register Bits multiples Kbytes (base to bound: LAS in LSIx_CTL ...
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... VMEbus. The figure below illustrates the translation process:. Offset [31..12] Figure 2.8 : Address Translation Mechanism for PCI Bus to VMEbus Transfers Translations beyond the 4 Gbyte limit will wrap around to the low address range. 2-54 A32 Image PCI [31..12] PCI [11..0] VME [31..12] VME [11..0] Tundra Semiconductor Corporation Universe II User Manual ...
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... Within each region, the upper 64Kbytes map to VMEbus A16 space, while the remaining portion of the 16 Mbytes maps to VMEbus A24 space. Note that no offsets are provided, so address information from the PCI transaction is mapped directly to the VMEbus. Tundra Semiconductor Corporation Slave Image Programming 2-55 ...
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... Places image in Memory or I/O Description separately sets each region for bits separately sets each region as supervisor or non-privileged separately sets each region as program or data Description enable bit for the image enable bit for posted writes for the image Tundra Semiconductor Corporation ...
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... Universe II User Manual BASE+400 0000 64 Kbytes BASE+3FF 0000 BASE+300 0000 BASE+2FF 0000 BASE+200 0000 BASE+1FF 0000 BASE+100 0000 BASE+0FF 0000 BASE+000 0000 Figure 2.9 : Memory Mapping in the Special PCI Target Image Tundra Semiconductor Corporation A16 3 A24 A16 2 A24 A16 1 A24 A16 0 A24 ...
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... A.108). An interrupt is generated on the VMEbus and/or PCI bus depending upon whether the VERR and VERR interrupts are enabled (see “Interrupt Handling” on page 2-68). The remaining entries of the offending transaction are purged from the FIFO. 2-58 Universe II User Manual Tundra Semiconductor Corporation ...
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... The log is acknowledged and made available to latch another error by clearing the corresponding status bit in the VINT_STAT or LINT_STAT registers. Should a second error occur before the CPU has the opportunity to acknowledge the first error, another bit in the logs is set to indicate this situation (M_ERR bit). Tundra Semiconductor Corporation Bus Error Handling 2-59 ...
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... The DP_D (Data Parity Detected) bit in the same register is only set if parity checking is enabled through the PERESP bit and the Universe II detects a parity error while it is PCI master (i.e. it asserts PERR# during a read transaction or receives PERR# during a write). 2-60 Universe II User Manual Tundra Semiconductor Corporation ...
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... SERR# is enabled or not, the Universe II does not respond to the access with DEVSEL#. Typically the master of the transaction times out with a Master-Abort master, the Universe II does not monitor SERR expected that a central resource on the PCI bus will monitor SERR# and take appropriate action. Tundra Semiconductor Corporation Bus Error Handling 2-61 ...
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... VMEbus sources, VIRQ[7:1], can only be mapped to the PCI interrupt outputs. Some internal sources (for example, error conditions or DMA activity) can be mapped to either bus. LINT [7:0] Figure 2.10 : Universe Interrupt Circuitry 2-62 Mapping Internal Interrupt and Enabling Handler Internal Sources Mapping and Enabling Tundra Semiconductor Corporation Universe II User Manual VRACFAIL# VRSYSFAIL# VRIQ#[7:1] VXIRQ#[7:1] ...
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... PCI specification. The other seven may require buffering if they are to be routed to PCI compliant interrupt lines. For most applications, however, the drive strength provided should be sufficient. PCI interrupts may be generated from multiple sources: • VMEbus sources of PCI interrupts - IRQ*[7:1] - SYSFAIL* - ACFAIL* Tundra Semiconductor Corporation Interrupt Generation 2-63 ...
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... Table A.73) ACFAIL ACFAIL SYSFAIL SW_INT SW_INT SW_IACK VERR VERR LERR LERR DMA DMA VIRQ7-1 VIRQ7-1 LM3-0 LM3-0 MBOX3-0 VOWN VOWN Universe II User Manual Status Bit in LINT_STAT (Table A.58) ACFAIL SYSFAIL SW_INT SW_IACK VERR LERR DMA VIRQ7-1 LM3-0 MBOX3-0 VOWN Tundra Semiconductor Corporation ...
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... Interrupts may be generated on any combination of VMEbus interrupt lines (IRQ*[7:1]) from multiple sources: • PCI sources of VMEbus interrupts - LINT#[7:0] • Internal sources of VMEbus interrupts - DMA - VMEbus bus error encountered - PCI Target-Abort or Master-Abort encountered - Mailbox register access - software interrupt Tundra Semiconductor Corporation Interrupt Generation 2-65 ...
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... VXIRQ2 etc. 2-66 Mapping Field in VINT_MAPx (Table A.63, Table A.64, Table A.74) N/A VERR VERR (Table A.64) LERR LERR (Table A.64) DMA DMA (Table A.64) MBOX3-0 (Table A.74) LINT7-0 LINT7-0 (Table A.74) SW_INT SW_INT(Table A.64) Universe II User Manual Status Bit in VINT_STAT (Table A.62) a SW_INT7-1 VERR LERR DMA MBOX3-0 LINT7-0 SW_INT Tundra Semiconductor Corporation ...
Page 95
... VMEbus interrupt. Since software interrupts are ROAK, the respective bits in the VINT_STAT register are cleared automatically on completion of the IACK cycle, simultaneously with the negation of the IRQ. Tundra Semiconductor Corporation Interrupt Generation 0 if S/W Interrupt Source 1 if Internal or LINT ...
Page 96
... As a VMEbus interrupt handler, the Universe II can monitor any or all of the VMEbus interrupt levels. It can also monitor SYSFAIL* and ACFAIL*, although IACK cycles are not generated for these inputs. Each interrupt is enabled through the LINT_EN register (Table A.57). 2-68 Universe II User Manual Tundra Semiconductor Corporation ...
Page 97
... Once the IACK cycle is complete and the STATUS/ID stored, an interrupt is generated to the PCI bus on one of LINT#[7:0] depending on the mapping for that VMEbus level in the LINT_MAP0 register. The interrupt is cleared and the VMEbus interrupt level is re-armed by clearing the correct bit in the LINT_STAT register. Tundra Semiconductor Corporation Interrupt Handling 2-69 ...
Page 98
... VMEbus master bus error interrupt and another through the standard PCI interrupt translation. Should an error occur during acquisition of a STATUS/ID, the VINT_STAT register (Table A.62) will show that both VIRQx, and VERR are active. 2-70 Universe II User Manual Tundra Semiconductor Corporation ...
Page 99
... Master-Abort VMEbus bus error VMEbus bus ownership granted Figure 2.12 shows the sources of interrupts, and the interfaces from which they originate. Interrupt handling for each one of these sources is described in the following subsections. Tundra Semiconductor Corporation May be Routed to: VMEbus PCI Bus Interrupt Handling 2-71 ...
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... DMA bidirectional FIFO PCI Bus Slave Channel posted writes FIFO coupled read logic Interrupt Channel Interrupt Handler DMA VME error VME ownership bit PCI error VME software interrupt Universe II User Manual VMEbus Interface VME Slave VME Master software IACK Tundra Semiconductor Corporation ...
Page 101
... The term “enable” is more meaningful with respect to the other fields in this register, i.e., excluding the software interrupts. Writing to the software interrupt fields of this register does not enable an interrupt, it triggers an inter- rupt. Tundra Semiconductor Corporation 1 This causes an interrupt to be generated on the corresponding ...
Page 102
... LINT_EN register (Table A.57) and mapped to a particular LINT# pin using the LINT_MAP1 register (Table A.60). A status bit in the LINT_STAT register (Table A.62) indicates when the interrupt source is active, and is used to clear the interrupt once it has been serviced. 2-74 Universe II User Manual Tundra Semiconductor Corporation ...
Page 103
... In order for an incoming VMEbus transaction to activate the location monitor of the Universe II, the location monitor must be enabled, the access must be within 4 kbytes of the location monitor base address (LM_BS, Table A.102), and it must be in the specified address space. Tundra Semiconductor Corporation Interrupt Handling 2-75 ...
Page 104
... When the Monarch detects an Auto-ID STATUS/ID on level expected to access the enabled CR/CSR space of the interrupter. From there it completes identification and configuration of the card. The Monarch functionality is typically implemented in software on one card in the VMEbus system. See “Automatic Slot Identification” on page 2-24. 2-76 Universe II User Manual Tundra Semiconductor Corporation ...
Page 105
... PCI bus and VMEbus. A final register contains status and control information for the transfer. While the DMA is active, the registers are locked against any changes so that any writes to the registers will have no impact. Tundra Semiconductor Corporation DMA Controller 2-77 ...
Page 106
... DLA and DVA registers should not be used, but the DTBC is valid (see “DMA Error Handling” on page 2-96 for details). At the end of a successful linked-list transfer, the DVA and DLA registers will point to the next address at the end of the transfer block, and the DTBC register will be zero. 2-78 Universe II User Manual Tundra Semiconductor Corporation ...
Page 107
... Universe II VMEbus Master will generate BLT transfers. The value of this bit only has meaning if the address space is A24 or A32 and the data width is not 64 bits. If the data width is 64 bits the Universe II may perform MBLT transfers independent of the state of the VCT bit. Tundra Semiconductor Corporation DMA Controller 2-79 ...
Page 108
... Otherwise, if the CHAIN bit is set, it loads into the DMA registers the command packet pointed to by the DCPP register and initiates the transfer describe there. 2-80 Universe II User Manual Tundra Semiconductor Corporation ...
Page 109
... VON boundary has been reached. Since the DMA operates in a round-robin fashion with the PCI Target Channel, and in a priority fashion with the Interrupt Channel, if either of these channels require ownership of the VMEbus, they will receive it at this time. Tundra Semiconductor Corporation DMA Controller 2-81 ...
Page 110
... The DMA then terminates, the HALT bit in the DGCS register is set, and, if enabled, an interrupt generated. After a stop or halt, the DMA can be restarted from the point it left off by setting the GO bit; but before it can be re-started, the STOP and HALT bits must both be cleared. 2-82 Universe II User Manual Tundra Semiconductor Corporation ...
Page 111
... Once the transfer described by the DVA, DLA, DTBC and DCTL registers has been completed, the DMA sits idle awaiting the next manual programming of the registers. Figure 2.13 describes the steps involved in operating the DMA in direct mode. Tundra Semiconductor Corporation DMA Controller 2-83 ...
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... Figure 2.13 : Direct Mode DMA transfers 2-84 Step 1: Program DGCS with tenure and interrupt requirements Step 2: Program source/destination addresses, & transfer size/attributes Step 4: Set GO bit Step 5: Await termination of DMA Normal No Termination? Yes More transfers required? No Done Universe II User Manual Handle error Tundra Semiconductor Corporation ...
Page 113
... It is recommended that a background timer also be initiated to time-out the transfer. This will ensure that the DMA has not been hung busy VMEbus, or other such system issues. Tundra Semiconductor Corporation DMA Controller 2-85 ...
Page 114
... This implies that the PROCESSED bit must be initially set for “0” by the user for use. This bit, when set to 1, indicates that this command packet has been disposed of by the DMA and its memory can be de-allocated or reused for another transfer description. 2-86 Universe II User Manual Tundra Semiconductor Corporation ...
Page 115
... NULL bit is set to “1” then the address in the command packet pointer is considered invalid and the DMA stops at the completion of the transfer described by the current command packet. Figure 2.15 outlines the steps in programming the DMA for linked-list operation. Tundra Semiconductor Corporation First Command Packet in Linked-List DCTL Register ...
Page 116
... This allows continuous programming of the packets without having to set-up or tear down packets later. 2-88 requirements Step 4 : Set GO bit of DMA Normal No handle error Termination? Yes Done Universe II User Manual Tundra Semiconductor Corporation ...
Page 117
... DGCS register polling the PROCESSED bits of the command packets recommended that a background timer also be initiated to time-out the transfer. This will ensure that the DMA has not been hung busy VMEbus, or other such system issues. Tundra Semiconductor Corporation DMA Controller 2-89 ...
Page 118
... DONE bit is set, and the ACT flag is cleared completes the transfers indicated by each command packet, the DMA sets the PROCESSED bit in that command packet before reading in the next command packet and processing its contents. 2-90 Universe II User Manual Tundra Semiconductor Corporation ...
Page 119
... DCPP register would point to the most recently programmed command packet, and the DTBC register would be zero. The DMA can be started on the new packet by simply clearing the DONE bit and setting the GO bit in the DGCS register Tundra Semiconductor Corporation DMA Controller 2-91 ...
Page 120
... DMAFIFO for a full transaction. The available space required for another burst read transaction is again 128 bytes. Since the VMEbus is typically much slower than the PCI bus, the DMAFIFO may fill frequently during 2-92 Universe II User Manual Tundra Semiconductor Corporation ...
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... Ownership” on page 2-81. To further control the DMA’s VMEbus ownership, the VOFF timer in the DGCS register can be used to program the DMA to remain off the VMEbus for a specified period when VMEbus tenure is relinquished. See “DMA VMEbus Ownership” on page 2-81. Tundra Semiconductor Corporation DMA Controller 2-93 ...
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... VMEbus. The Universe II maintains VMEbus ownership until: • the DMAFIFO is full, • the DMA block is complete, • the DMA is stopped, • a linked list is halted, • the DMA encounters an error, or • the VMEbus tenure limit is reached (VON in the DGCS register). 2-94 Universe II User Manual Tundra Semiconductor Corporation ...
Page 123
... Table 2.17 below. Setting the enable bit enables the corresponding interrupt source. Table 2.17 : DMA Interrupt Sources and Enable Bits Interrupt Source Stop Request Halt Request DMA Completion PCI Target-Abort or Master-Abort VMEbus Error Tundra Semiconductor Corporation DMA Controller Enable Bit INT_STOP INT_HALT INT_DONE INT_LERR INT_VERR ...
Page 124
... This section describes how the Universe II responds to errors involving the DMA, and how the user can recover from them. As described below, the software source of a DMA error is a protocol, and the hardware source of a DMA error is a VMEbus error, or PCI bus Target-Abort or Master-Abort. 2-96 Universe II User Manual Enable Bit INT_M_ERR Tundra Semiconductor Corporation ...
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... DMA is writing data to the destination bus, the DMA stops writing to the destination bus, and it also stops reading from the source bus. The error bit in the DGCS register is set and an interrupt asserted (if enabled). Tundra Semiconductor Corporation DMA Controller 2-97 ...
Page 126
... In this case, the error will have occurred up to 256 bytes before: the original address plus the byte count. 2-98 Universe II User Manual Tundra Semiconductor Corporation ...
Page 127
... DTBC register to the original value in the DLA register. 6. Add the difference between the original value in the DTBC and the new value in the DTBC register to the original value in the DVA register. 7. Clear the status flags. 8. Restart the DMA (see “DMA Initiation” on page 2-80). Tundra Semiconductor Corporation DMA Controller 2-99 ...
Page 128
... The Universe II registers are little-endian. The access mechanisms for the UCSR are different depending upon whether the register space is accessed from the PCI bus or VMEbus. Register access from the PCI bus and VMEbus is discussed below. 2-100 Universe II User Manual Tundra Semiconductor Corporation ...
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... SPACE (PCICS) Figure 2.16 : Universe II Control and Status Register Space 2.9.2 Register Access from the PCI Bus There are two mechanisms to access the UCSR space from the PCI bus: through Configuration space or through PCI Memory or I/O space (Table A.6). Tundra Semiconductor Corporation Registers 4 Kbytes 2-101 ...
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... Status Registers UNIVERSE DEVICE SPECIFIC REGISTERS PCI CONFIGURATION Accessible through PCI Configuration Cycle Figure 2.17 : PCI Bus Access to UCSR as Memory or I/O Space 2-102 (VCSR) All 4 Kbytes (UDSR) Accessible as Memory or I/O Space SPACE (PCICS) PCI_BS Tundra Semiconductor Corporation Universe II User Manual 4 Gbytes of Memory or I/O Space ...
Page 131
... When an external PCI master locks the register block of the Universe II, an access to the register block from the VMEbus will not terminate with the assertion of DTACK* until the register block is unlocked. Hence a prolonged lock of the register block by a PCI resource may cause the VMEbus to timeout with a BERR*. Tundra Semiconductor Corporation Registers 2-103 ...
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... Option Descriptions” on page 2-117). 2-104 Register Bits VAS in Table A.103 EN in Table A.103 PGM in Table A.103 Universe II User Manual Description one of A16, A24, A32 lowest address in the 4Kbyte slave image enables VMEbus register access image Supervisor and/or Non-Privileged Program and/or Data Tundra Semiconductor Corporation ...
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... Universe II User Manual VMEbus Configuration and Status Registers (VCSR) UNIVERSE DEVICE SPECIFIC REGISTERS (UDSR) PCI CONFIGURATION SPACE (PCICS) Figure 2.18 : UCSR Access from the VMEbus Register Access Image Tundra Semiconductor Corporation Total Memory in A16, A24 or A32 Address Space 4 Kbytes of UCSR VRAI_BS Registers 2-105 ...
Page 134
... UCSR is required, then the VMEbus master should lock the Universe II through the use of ADOH. This prevents an external PCI Master from accessing the registers of the Universe II until VMEbus BBSY* is negated. It also prevents other VMEbus masters from accessing the Universe II registers. 2-106 Universe II User Manual Tundra Semiconductor Corporation ...
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... Universe II User Manual VMEbus Configuration and Status Registers UNIVERSE DEVICE SPECIFIC REGISTERS PCI CONFIGURATION Mapped to PCI Figure 2.19 : UCSR Access in VMEbus CR/CSR Space Tundra Semiconductor Corporation (VCSR) 4 Kbytes (UDSR) of UCSR SPACE (PCICS) VCSR_BS Registers 512 Kbytes of VMEbus CR/CSR Space (Portion of 16 Mbyte ...
Page 136
... PCI bus, and read-only from the VMEbus, and the two other mailboxes as read/write from the VMEbus and read-only from the PCI bus. This eliminates the need to implement locking. The Universe II provides semaphores which can be also be used to synchronise access to the mailboxes. Semaphores are described in the next section. 2-108 Universe II User Manual Tundra Semiconductor Corporation ...
Page 137
... Special Cycle completes. A separate process that intends to modify the same address would need to obtain the semaphore before proceeding (it need not verify the state of the SCYC[1:0] bit). This mechanism requires that processes know which addresses might be accessed through the Special Cycle Generator. Tundra Semiconductor Corporation Registers 2-109 ...
Page 138
... Resets the Universe II from the PCI bus. VMEbus Reset Causes Universe II to assert VXSYSRST Initiator PCI Bus Reset Output JTAG Test Reset Provides asynchronous initialization of the TAP controller in the Universe II. Universe II User Manual a Effects options. Resets PCI resources Tundra Semiconductor Corporation ...
Page 139
... Table A.126 SYSFAIL VCSR_CLR RESET Table A.125 SYSFAIL More detailed information about the effects of various reset events is provided in the next section. Tundra Semiconductor Corporation Function W Software PCI Reset 0=No effect, 1=Initiate LRST# A read always returns 0. W Software VMEbus SYSRESET 0=No effect, 1=Initiate SYSRST* A read always returns 0 ...
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... LRST# may be cleared by writing 1 to the RESET bit in the 2-112 a,b PWRRST# PWRRST#, or VRSYSRST# PWRRST#, RST# or VRSYSRST# PWRRST#, or VRSYSRST# PWRRST#, or VME_RESET#, or SW_SYSRST bit in MISC_CTL register PWRRST#, or SW_LRST bit in MISC_CTL register, or RESET bit in VCSR_SET register . CSR_CLR register Universe II User Manual Reset Source c Tundra Semiconductor Corporation ...
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... Note 1: On PWRRST#, options are loaded from pins. On SYSRST and RST#, options are loaded from values that were latched at the previous PWRRST#. Note 2:Refer to Appendix-A to find the effects of various reset events. Tundra Semiconductor Corporation VME Services (VME Arbiter, VMEbus timer, VCSR registers) ...
Page 142
... VCSR_CLR register. The FAIL bit in each of these registers is a status bit and is set by the software to indicate board failure. Figure 2.21 : Resistor-Capacitor Circuit Ensuring Power-Up Reset Duration 2-114 Universe II User Manual 47 K PWRRST Tundra Semiconductor Corporation ...
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... Table 2.22 lists the power-up options of the Universe II, the pins which determine the options, and the register settings that are set by this option. Each option is described in more detail in “Power-up Option Descriptions” on page 2-117. Tundra Semiconductor Corporation Utility Functions (or active drive) is 2-115 ...
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... LSI0_BS BS LSI0_BD BD PCI_BS0, SPACE See Table A.6 and PCI_BS1 MISC_STAT LCLSIZE PCI_CSR BM Universe II User Manual Default Pins disabled VA[31] A16 VA[30:29] 0x00 VA[28:21] memory VA[20] 0x00 VA[19:15] disabled VD[30] disabled VD[29 000 disabled VD[28] enabled VBGIN[3]* asserted VD[27] disabled VA[13] memory VA[12] A16 VA[11:10] 0x0 VA[9:6] 0x0 VA[5:2] VA[1] Table A.7 32-bit REQ64# disabled VA[14] Tundra Semiconductor Corporation ...
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... CR/CSR space can be mapped to memory or I/O space with a 5-bit offset. This allows mapping to any 128Mbyte page on the PCI bus. As part of this implementation, ensure that the PCI Master Interface is enabled through the MAST_EN bit power-up option (see below) or configured through a register access before accessing configuration ROM. Tundra Semiconductor Corporation BS [31:24] BS [23:16] 0 ...
Page 146
... VMEbus cycles in the non-privileged data space will be generated. This option would typically be used to access permits the use of Boot ROM on another card in the VMEbus system. 2-118 Universe II User Manual Tundra Semiconductor Corporation ...
Page 147
... A[31:1] and D[31:27]) to their appro- priate state. Caution: The internal pull-downs are very weak. The leakage current on many ! transceivers may be sufficient to override these pull-downs. To ensure proper operation designers should ensure power-up option pins will go to the correct state. Tundra Semiconductor Corporation Utility Functions 2-119 ...
Page 148
... Because of the power-up configuration, the VMEbus buffers are not enabled until several CLK64 periods after release of SYSRST* (approximately 45 ns). Allowing for worst case backplane skew of 25 ns, the Universe II will not be prepared to receive a slave access until 70 ns after release of SYSRST*. 2-120 Universe II User Manual power-up options Tundra Semiconductor Corporation ...
Page 149
... Table 2.24 : Manufacturing Pin Requirements for Normal Operating Mode Pin Name TMODE[2] V (or pulled-down if board tests will occasionally be performed, see “Auxiliary Test SS TMODE[1] TMODE[0] PLL_TESTSEL ENID PLL_TESTOUT VCOCTL Tundra Semiconductor Corporation Utility Functions Pin Value Modes” on page 2-122 N 2-121 ...
Page 150
... For High Impedance mode, the values of the TMODE pins are also latched during the active part of PWRRST#. All outputs are tristated in this mode, except for the VXSYSFAIL output pin. 2-122 Universe II User Manual TMODE[2:0] PLL_TESTSEL 000 001 010 011 100 101 110 111 Tundra Semiconductor Corporation 0/1 1 ...
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... IDCODE register which returns 32'b01e201d. The following external pins are not part of the boundary scan register: LCLK, PLL_TESTOUT, PLL_TESTSEL, TMODE[3:0], and VCOCTL. A BSDL file is available upon request from Tundra Semiconductor Corporation. 2.10.5 Clocks CLK64 MHz clock that is required by the Universe II in order to synchronize internal Universe II state machines and to produce the VMEbus system clock (VSYSCLK) when the Universe II is system controller (SYSCON) ...
Page 152
... Utility Functions 2-124 Universe II User Manual Tundra Semiconductor Corporation ...
Page 153
... When the Universe II is driving lines on the VMEbus, this signal is driven high; when the VMEbus is driving the Universe II, this signal is driven low. VAS# VMEbus Address Strobe – the falling edge of VAS# indicates a valid address on the bus. By continuing to assert VAS#, ownership of the bus is maintained during a RMW cycle. Tundra Semiconductor Corporation Input Bidirectional Output Bidirectional ...
Page 154
... VMEbus Data Transfer Acknowledge – VDTACK# driven low indicates that the addressed slave has responded to the transfer. The Universe II always rescinds DTACK tristated once the initiating master negates AS*. 3-2 (Continued) Output Output Input Output Bidirectional Output Bidirectional Output Bidirectional Tundra Semiconductor Corporation Universe II User Manual ...
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... Bus Grant signals. Also monitored by requester in ROR mode. VRIRQ# [7:1] VMEbus Receive Interrupts 7 through 1 – these interrupts can be mapped to any of the Universe II’s PCI interrupt outputs. VRIRQ7-1# are individually maskable, but cannot be read. Tundra Semiconductor Corporation (Continued) Bidirectional Input Output ...
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... VMEbus System Failure – asserted by the Universe II during reset and plays a role in VME64 Auto ID. VXSYSRST VMEbus System Reset – the Universe II output for SYSRST*. 3-4 (Continued) Input Input Output Bidirectional Output Bidirectional Output Output Output Output Output Output Tundra Semiconductor Corporation Universe II User Manual ...
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... PCI Clock – provides timing for all transactions on the PCI bus. PCI signals are sampled on the rising edge of CLK, and all timing parameters are defined relative to this signal. The PCI clock frequency of the Universe II II must be between 25 and 33MHz. Lower frequencies will result in invalid VME timing. Tundra Semiconductor Corporation Bidirectional Bidirectional ...
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... PCI Reset Input—resets the Universe II from the PCI bus. SERR# System Error – reports address parity errors or any other system error. 3-6 (Continued) Bidirectional Output Bidirectional Bidirectional Bidirectional Output Input Input Output Bidirectional Input Bidirectional Tundra Semiconductor Corporation Universe II User Manual ...
Page 159
... JTAG Test Reset – provides asynchronous initialization of the TAP controller in the Universe II. Tie to ground if JTAG is not used in the system. VCOCTL Manufacturing testing, tie to ground for normal operation VME_RESET# VMEbus Reset Input — generates a VME bus system reset. Tundra Semiconductor Corporation (Continued) Bidirectional Input Input Output ...
Page 160
... PCI Bus Signals 3-8 Universe II User Manual Tundra Semiconductor Corporation ...
Page 161
... A numbered suffix indicates the current rating of the output (in mA). Analog I I TTL TTL SCH 3S Tundra Semiconductor Corporation Analog input signal Input only Input and output Output only Open drain output Pulled-down internally Pulled-up internally Totem pole output Input with TTL thresholds Schmitt trigger input with TTL thresholds Tri– ...
Page 162
... T– T– With no pull–up resistor ( OUT OUT DD Tundra Semiconductor Corporation Universe II User Manual Tested at 0°C to 70°C Min Max 2 0. –0.3 V 0.8V –0.3 V 0.3V DD – 2.4 V – 0.7V DD 0.8 V – ...
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... K4 IRDY# AC15 V12 LCLK AA3 W3 LOCK# AA23 T18 LRST PAR P8 L1 PAR64 AE5 W4 PERR# AB4 W5 PLL_TESTOUT AB2 V1 Tundra Semiconductor Corporation DC Characteristics and Pin Assignments Output I OL Type Input Type Type (mA) I/O TTL 3S 6 I/O TTL 3S 6 I/O TTL TTL – – I/O – ...
Page 164
... JTAG Test Mode Select –2 PCI Target Ready – JTAG Test Reset –3 VMEbus Address Pins –3 VMEbus Address Modifier Signals –6 VMEbus AM Signal Direction Control –3 VMEbus Address Strobe –6 VMEbus AS Direction Control –12 VMEbus Address Direction Control Tundra Semiconductor Corporation ...
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... VIACKO# L21 H17 VLWORD# K14 C11 VME_RESET# V22 T19 VOE# B12 C10 VRACFAIL# P18 M16 VRBBSY VRBERR Tundra Semiconductor Corporation DC Characteristics and Pin Assignments Output I OL Type Input Type Type (mA) O – – – TT (PD) O – – ...
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... Signal – VMEbus Receive SYSRESET* Signal –6 SYSCON signals direction control –6 DTACK/BERR direction control –3 VMEbus SYSCLK Signal –3 VMEbus Write –3 VMEbus Transmit BBSY* Signal –3 VMEbus Transmit Bus Error (BERR*) –3 VMEbus Transmit Bus Request Tundra Semiconductor Corporation ...
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... T17 AD [10] AC21 V19 AD [11] AB20 V15 AD [12] AC19 W18 AD [13] AA17 V14 AD [14] AA15 U13 AD [15] U15 R12 AD [16] AE11 U10 Tundra Semiconductor Corporation Output I OL Type Input Type Type (mA) O – – – Signal PBGA AD [32] ...
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... AD [31] P10 L4 4-8 Universe II User Manual Signal PBGA CBGA AD [49] Y12 W9 AD [50] AC11 R9 AD [51] V10 Y4 AD [52] AB10 R8 AD [53] AA9 U7 AD [54] AB8 T6 AD [55] AB6 V4 AD [56 [57 [58] AA1 T1 AD [59 [60 [61 [62 [63 Tundra Semiconductor Corporation ...
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... A19 E14 VA [12] B18 B14 VA [13] F16 A16 VA [14] E17 D14 VA [15] A21 B17 VA [16] F18 B15 a. All VA pins have an internal pull-down. Tundra Semiconductor Corporation a Signal PBGA CBGA VA [17] D18 B16 VA [18] C19 C15 VA [19] B20 D17 VA [20] B22 D15 VA [21] ...
Page 170
... Signal PBGA VD [16 [17 [18 [19 [20 [21 [22 [23 [24 [25 [26 [27 [28 [29 [30 [31] E9 Tundra Semiconductor Corporation Universe II User Manual CBGA ...
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... Table 4.7 and Table 4.8 below are tables that map pin numbers to signal ! names. These tables should not be read as figures. For layout purposes, please see Appendix-G. Tundra Semiconductor Corporation DC Characteristics and Pin Assignments V Pins DD ...
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Table 4.7 : Pinout for 313-pin Plastic BGA Package VD[22] VD[19] VD[9] VD[5] 2 VD[18] VD[14] VD[13] 3 VD[23] VD[21] VD[20] VD[12] 4 VD[26] VDD VD[15] 5 VD[30] VD[24] VDD VD[17] 6 VD[27] ...
Page 173
Table 4.8 : Pinout for 324–pin Ceramic BGA Package VSS VD[1] VD[7] 2 VSS VD[22] VD[9] VD[16] 3 VD[21] VD[28] VDD VD[15] VD[19] 4 VDD VD[26] VD[24] VD[13] VD[20] 5 VD[30] VD[23] VDD VDD ...
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... DC Characteristics and Pin Assignments 4-14 Universe II User Manual Tundra Semiconductor Corporation ...
Page 175
... VMEbus Configuration and Status Registers UNIVERSE DEVICE SPECIFIC REGISTERS PCI CONFIGURATION SPACE (PCICS) Figure A.1 : UCSR Access Mechanisms The bit combinations listed as "Reserved" must not be programmed. All bits listed as "Reserved" must read back a value of zero. Tundra Semiconductor Corporation Registers (VCSR) (UDSR) 4 Kbytes App A-1 ...
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... PCI Unimplemented PCI Reserved PCI Reserved PCI Unimplemented Reserved Reserved Reserved Universe II User Manual Name PCI_ID PCI_CSR PCI_CLASS PCI_MISC0 PCI_BS0 PCI_BS1 PCI_MISC1 LSI0_CTL LSI0_BS LSI0_BD LSI0_TO LSI1_CTL LSI1_BS LSI1_BD LSI1_TO LSI2_CTL LSI2_BS LSI2_BD LSI2_TO LSI3_CTL LSI3_BS LSI3_BD LSI3_TO Tundra Semiconductor Corporation ...
Page 177
... PCI Target Image 7 Translation Offset Register 1EC-1FC 200 DMA Transfer Control Register 204 DMA Transfer Byte Count Register 208 DMA PCI Bus Address Register 20C 210 DMA VMEbus Address Register 214 Tundra Semiconductor Corporation (Continued) Register Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Registers ...
Page 178
... Reserved Universe II User Manual Name DCPP DGCS D_LLUE LINT_EN LINT_STAT LINT_MAP0 LINT_MAP1 VINT_EN VINT_STAT VINT_MAP0 VINT_MAP1 STATID V1_STATID V2_STATID V3_STATID V4_STATID V5_STATID V6_STATID V7_STATID LINT_MAP2 VINT_MAP2 MBOX0 MBOX1 MBOX2 MBOX3 SEMA0 SEMA1 MAST_CTL MISC_CTL MISC_STAT USER_AM VSI0_CTL VSI0_BS Tundra Semiconductor Corporation ...
Page 179
... VMEbus Slave Image 4 Bound Address Register F9C VMEbus Slave Image 4 Translation Offset Register FA0 FA4 VMEbus Slave Image 5 Control Register FA8 VMEbus Slave Image 5 Base Address Register FAC VMEbus Slave Image 5 Bound Address Register Tundra Semiconductor Corporation (Continued) Register Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...
Page 180
... VMEbus CSR Bit Clear Register FF8 VMEbus CSR Bit Set Register FFC VMEbus CSR Base Address Register App A-6 (Continued) Register Reserved Reserved Reserved VME CR/CSR Reserved Universe II User Manual Name VSI5_TO VSI6_CTL VSI6_BS VSI6_BD VSI6_TO VSI7_CTL VSI7_BS VSI7_BD VSI7_TO VCSR_CLR VCSR_SET VCSR_BS Tundra Semiconductor Corporation ...
Page 181
... Table A.2 : PCI Configuration Space ID Register (PCI_ID) Register Name: PCI_ID Bits 31-24 23-16 15-08 07-00 PCI_ID Description Name Type Reset By DID[15:0] R all VID[15:0] R all Tundra Semiconductor Corporation Function DID DID VID VID Reset State 0 Device ID - Tundra allocated device identifier 10E3 Vendor ID - PCI SIG allocated vendor identifier Registers Offset:000 Function App A-7 ...
Page 182
... Error Response bit is set the master of transaction in which it asserts PERR#, or the addressed target asserts PERR#. 0 Target Fast Back to Back Capable Universe II cannot accept Back to Back cycles from a different agent. Universe II User Manual Offset:004 DEVSEL DP_D MFBBC SERR_EN BM MS IOS Function Tundra Semiconductor Corporation ...
Page 183
... If the VCSR or LSI0 power-up options are enabled, these bits are not diabled after reset. The Universe II only rejects PCI addresses with parity errors in the event that both the PERESP and SERR_EN bits are programmed to a value of 1. Tundra Semiconductor Corporation Reset State 0 ...
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... Reset State 06 Base Class Code The Universe II is defined as a PCI bridge device 80 Sub Class Code The Universe II sub-class is "other bridge device" 00 Programming Interface The Universe II does not have a standardized register-level programming interface 01 Revision ID Tundra Semiconductor Corporation Universe II User Manual Offset:008 Function ...
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... CCODE R all MFUNCT R all LAYOUT R all LTIMER [7:3] R/W all The Universe II is not a multi-function device. Tundra Semiconductor Corporation Function PCI Reserved LAYOUT LTIMER PCI Unimplemented Reset State 0 The Universe II is not BIST Capable 0 Start BIST The Universe II is not BIST capable 0 Completion Code ...
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... A write must occur to this register before the Universe II Device Specific Registers can be accessed. This write can be performed with a PCI configuration transaction or a VMEbus register access. App A-12 Function Reset State 0 Base Address Power-up PCI Bus Address Space Option 0=Memory, 1=I/O Universe II User Manual Offset:010 SPACE Function Tundra Semiconductor Corporation ...
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... A write must occur to this register before the Universe II Device Specific Registers can be accessed. This write can be performed with a PCI configuration transaction or a VMEbus register access. The SPACE bit in this register is an inversion of the SPACE field in PCI_BS0. Tundra Semiconductor Corporation Function BS BS ...
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... Maximum Latency: This device has no special latency all requirements 00000011 Minimum Grant:.250 ns units all 00000001 Interrupt Pin: Universe II pin INT# [0] has a PCI compliant all I/O buffer 0 Interrupt Line: used by some PCI systems to record interrupt all routing information Universe II User Manual Offset:03C Function Tundra Semiconductor Corporation ...
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... If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64-bit, the Universe II may perform MBLT transfers independent of the state of the VCT bit. The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I/O Space, forcing all transactions through this image to be coupled. Tundra Semiconductor Corporation Function Reserved Reserved ...
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... The base address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution. PCI Target Images and 7 have a 64Kbyte resolution. App A-16 Function Reserved Reset State Power-up Base Address Option 0 Base Address Universe II User Manual Offset:104 Reserved Function Tundra Semiconductor Corporation ...
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... If the bound address is 0, then the addresses decoded are those greater than or equal to the base address. The bound address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution. PCI Target Images and 7 have a 64Kbyte resolution. Tundra Semiconductor Corporation Function BD BD ...
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... Address bits [31:12] generated on the VMEbus in response to an image decode are a two’s complement addition of address bits [31:12] on the PCI Bus and bits [31:12] of the image’s translation offset. App A-18 Function Reserved Reset State 0 Translation Offset Universe II User Manual Offset:10C Reserved Function Tundra Semiconductor Corporation ...
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... If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64-bit, the Universe II may perform MBLT transfers independent of the state of the VCT bit. The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I/O Space, forcing all transactions through this image to be coupled. Tundra Semiconductor Corporation Function Reserved Reserved ...
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... Table A.14 : PCI Target Image 1 Base Address Register (LSI1_BS) Register Name: LSI1_BS Bits 31-24 23-16 15-08 07-00 LSI1_BS Description Name Type Reset By BS[31:16] R/W all The base address specifies the lowest address in the address range that will be decoded. App A-20 Function BS BS Reserved Reserved Reset State 0 Base Address Tundra Semiconductor Corporation Universe II User Manual Offset:118 Function ...
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... If the bound address is 0, then the addresses decoded are those greater than or equal to the base address. The bound address for PCI Target Image 0 and PCI Target Image 4 have a 4Kbyte resolution. PCI Target Images and 7 have a 64Kbyte resolution. Tundra Semiconductor Corporation Function BD BD ...
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... Address bits [31:16] generated on the VMEbus in response to an image decode are a two’s complement addition of address bits [31:16] on the PCI Bus and bits [31:16] of the image’s translation offset. App A-22 Function TO TO Reserved Reserved Reset State 0 Translation offset Tundra Semiconductor Corporation Universe II User Manual Offset:120 Function ...
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... If VAS bits are programmed to A24 or A32 and the VDW bits are programmed for 64-bit, the Universe II may perform MBLT transfers independant of the state of the VCT bit. The setting of the PWEN bit is ignored if the LAS bit is programmed for PCI Bus I/O Space, forcing all transactions through this image to be coupled. Tundra Semiconductor Corporation Function Reserved Reserved ...
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... Table A.18 : PCI Target Image 2 Base Address Register (LSI2_BS) Register Name: LSI2_BS Bits 31-24 23-16 15-08 07-00 LSI2_BS Description Name Type Reset By BS[31:16] R/W all The base address specifies the lowest address in the address range that will be decoded. App A-24 Function BS BS Reserved Reserved Reset State 0 Base Address Tundra Semiconductor Corporation Universe II User Manual Offset:12C Function ...
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... The addresses decoded in a slave image are those which are greater than or equal to the base address and less than the bound register. If the bound address is 0, then the addresses decoded are those greater than or equal to the base address. Tundra Semiconductor Corporation Function BD ...
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... Address bits [31:16] generated on the VMEbus in response to an image decode are a two’s complement addition of address bits [31:16] on the PCI Bus and bits [31:16] of the image’s translation offset. App A-26 Function TO TO Reserved Reserved Reset State 0 Translation offset Tundra Semiconductor Corporation Universe II User Manual Offset:134 Function ...