CAT28C16A CATALYST [Catalyst Semiconductor], CAT28C16A Datasheet

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CAT28C16A

Manufacturer Part Number
CAT28C16A
Description
16K-Bit CMOS PARALLEL E2PROM
Manufacturer
CATALYST [Catalyst Semiconductor]
Datasheet

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CAT28C16A
16K-Bit CMOS PARALLEL E
FEATURES
DESCRIPTION
The CAT28C16A is a fast, low power, 5V-only CMOS
Parallel E
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V
eliminate additional timing and protection hardware.
DATA Polling signals the start and end of the self-timed
write cycle. Additionally, the CAT28C16A features hard-
ware write protection.
BLOCK DIAGRAM
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Fast Read Access Times: 200 ns
Low Power CMOS Dissipation:
–Active: 25 mA Max.
–Standby: 100 A Max.
Simple Write Operation:
–On-Chip Address and Data Latches
–Self-Timed Write Cycle with Auto-Clear
Fast Write Cycle Time: 10ms Max
A 4 –A 10
A 0 –A 3
2
V CC
PROM organized as 2K x 8-bits. It requires a
WE
CE
OE
CC
power up/down write protection
ADDR. BUFFER
INADVERTENT
ADDR. BUFFER
PROTECTION
TIMER
& LATCHES
CONTROL
& LATCHES
LOGIC
WRITE
2
PROM
1
DATA POLLING
HIGH VOLTAGE
The CAT28C16A is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 10,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 24-pin DIP and SOIC or 32-pin PLCC pack-
ages.
GENERATOR
DECODER
COLUMN
End of Write Detection: DATA
Hardware Write Protection
CMOS and TTL Compatible I/O
10,000 Program/Erase Cycles
10 Year Data Retention
Commercial, Industrial and Automotive
Temperature Ranges
DECODER
ROW
DATA
DATA
DATA
DATA Polling
I/O BUFFERS
I/O 0 –I/O 7
2,048 x 8
E
ARRAY
2
PROM
Doc. No. 25033-00 2/98
5089 FHD F02

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CAT28C16A Summary of contents

Page 1

... Simple Write Operation: –On-Chip Address and Data Latches –Self-Timed Write Cycle with Auto-Clear Fast Write Cycle Time: 10ms Max DESCRIPTION The CAT28C16A is a fast, low power, 5V-only CMOS 2 Parallel E PROM organized 8-bits. It requires a simple interface for in-system programming. On-chip ...

Page 2

... CAT28C16A PIN CONFIGURATION DIP Package (P) SOIC Package (J, I I/O 6 I ...

Page 3

ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. – +125 C Storage Temperature ....................... – +150 C Voltage on Any Pin with (2) Respect to Ground ........... –2. with Respect to Ground ............... –2.0V ...

Page 4

... CAT28C16A A.C. CHARACTERISTICS, Read Cycle 10%, unless otherwise specified. CC Symbol t Read Cycle Time Access Time CE t Address Access Time Access Time OE ( Low to Active Output LZ ( Low to Active Output OLZ (1)( High to High-Z Output HZ (1)( High to High-Z Output ...

Page 5

A.C. CHARACTERISTICS, Write Cycle 10%, unless otherwise specified. CC Symbol t Write Cycle Time WC t Address Setup Time AS t Address Hold Time Setup Time Hold Time CH (2) t ...

Page 6

... CAT28C16A DEVICE OPERATION Read Data stored in the CAT28C16A is transferred to the data bus when WE is held high, and both OE and CE are held Figure 3. Read Cycle ADDRESS DATA OUT Figure 4. Byte Write Cycle [WE Controlled] ADDRESS OES WE DATA OUT DATA IN Doc ...

Page 7

Byte Write A write cycle is executed when both CE and WE are low, and OE is high. Write cycles can be initiated using either WE or CE, with the address input being latched on the falling edge of WE ...

Page 8

... Number * -40˚C to +125˚C is available upon request Notes: (1) The device used in the above example is a CAT28C16ANI-20T (PLCC, Industrial temperature, 200 ns Access Time, Tape & Reel). Doc. No. 25033-00 2/98 teristics), provides delay before a write sequence, after V (3) Write inhibit is activated by holding any one of OE low, CE high or WE high ...

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