CAT28C64B CATALYST [Catalyst Semiconductor], CAT28C64B Datasheet

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CAT28C64B

Manufacturer Part Number
CAT28C64B
Description
64K-Bit CMOS PARALLEL E2PROM
Manufacturer
CATALYST [Catalyst Semiconductor]
Datasheet

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CAT28C64B
64K-Bit CMOS PARALLEL E
FEATURES
DESCRIPTION
The CAT28C64B is a fast, low power, 5V-only CMOS
Parallel E
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and V
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28C64B features hardware and software write pro-
tection.
BLOCK DIAGRAM
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Fast Read Access Times:
– 120/150ns
Low Power CMOS Dissipation:
– Active: 25 mA Max.
– Standby: 100 A Max.
Simple Write Operation:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
Fast Write Cycle Time:
– 5ms Max.
CMOS and TTL Compatible I/O
Hardware and Software Write Protection
A 5 –A 12
A 0 –A 4
V CC
WE
OE
CE
2
PROM organized as 8K x 8-bits. It requires a
CC
power up/down write protection
ADDR. BUFFER
ADDR. BUFFER
INADVERTENT
PROTECTION
TIMER
& LATCHES
CONTROL
& LATCHES
LOGIC
WRITE
2
PROM
DATA POLLING
HIGH VOLTAGE
1
TOGGLE BIT
GENERATOR
DECODER
COLUMN
The CAT28C64B is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC-
approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC, or, 32-
pin PLCC package .
DECODER
AND
Automatic Page Write Operation:
– 1 to 32 Bytes in 5ms
– Page Load Timer
End of Write Detection:
– Toggle Bit
– DATA
100,000 Program/Erase Cycles
100 Year Data Retention
ROW
Commercial, Industrial and Automotive
Temperature Ranges
DATA
DATA
DATA Polling
DATA
I/O BUFFERS
I/O 0 –I/O 7
8,192 x 8
E
ARRAY
2
PROM
32 BYTE PAGE
Doc. No. 25006-0A 2/98 P-1
REGISTER
5094 FHD F02

Related parts for CAT28C64B

CAT28C64B Summary of contents

Page 1

... Fast Write Cycle Time: – 5ms Max. CMOS and TTL Compatible I/O Hardware and Software Write Protection DESCRIPTION The CAT28C64B is a fast, low power, 5V-only CMOS 2 Parallel E PROM organized 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with ...

Page 2

PIN CONFIGURATION DIP Package ( ...

Page 3

ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ................. – +125 C Storage Temperature ....................... – +150 C Voltage on Any Pin with (2) Respect to Ground ........... –2. with Respect to Ground ............... –2.0V ...

Page 4

D.C. OPERATING CHARACTERISTICS 10%, unless otherwise specified. CC Symbol Parameter I V Current (Operating, TTL ( Current (Operating, CMOS) CCC Current (Standby, TTL ( Current (Standby, ...

Page 5

A.C. CHARACTERISTICS, Read Cycle 10%, unless otherwise specified. CC Symbol Parameter t Read Cycle Time RC CE Access Time Address Access Time AA OE Access Time t OE (1) CE Low to Active Output ...

Page 6

A.C. CHARACTERISTICS, Write Cycle 10%, unless otherwise specified. CC Symbol Parameter t Write Cycle Time WC t Address Setup Time AS t Address Hold Time Setup Time Hold Time CH (2) ...

Page 7

... DEVICE OPERATION Read Data stored in the CAT28C64B is transferred to the data bus when WE is held high, and both OE and CE are held low. The data bus is set to a high impedance state when either goes high. This 2-line control architec- ture can be used to eliminate bus contention in a system environment ...

Page 8

... Page Write The page write mode of the CAT28C64B (essentially an extended BYTE WRITE mode) allows from bytes of data to be programmed within a single E cycle. This effectively reduces the byte-write time by a factor of 32. Following an initial WRITE operation (WE pulsed low, for t , and then high) the page write mode can begin by ...

Page 9

DATA Polling DATA polling is provided to indicate the completion of write cycle. Once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on I/O are ...

Page 10

... AC charac- INIT performed. The device is shipped from Catalyst with the software protection NOT ENABLED (the CAT28C64B is in the standard operating mode). Figure 10. Write Sequence for Deactivating Software Data Protection (1) ...

Page 11

... ID * -40˚C to +125˚C is available upon request Notes: (1) The device used in the above example is a CAT28C64BNI-15T (PLCC, Industrial temperature, 150 ns Access Time, Tape & Reel). To allow the user the ability to program the device with PROM programmer (or for testing purposes) there is a software command sequence for deactivating the data protection ...

Page 12

Doc. No. 25006-0A 2/98 P-1 12 ...

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