CAT28F010 CATALYST [Catalyst Semiconductor], CAT28F010 Datasheet

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CAT28F010

Manufacturer Part Number
CAT28F010
Description
1 Megabit CMOS Flash Memory
Manufacturer
CATALYST [Catalyst Semiconductor]
Datasheet

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CAT28F010
1 Megabit CMOS Flash Memory
FEATURES
DESCRIPTION
The CAT28F010 is a high speed 128K x 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E
Erase are performed through an operation and verify
algorithm. The instructions are input via the I/O bus,
BLOCK DIAGRAM
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Fast Read Access Time: 70/90/120 ns
Low Power CMOS Dissipation:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 A max (CMOS levels)
High Speed Programming:
–10 s per byte
–2 Sec Typ Chip Program
0.5 Seconds Typical Chip-Erase
12.0V
Stop Timer for Program/Erase
A 0 –A 16
5% Programming and Erase Voltage
WE
OE
CE
2
PROM devices.
VOLTAGE VERIFY
SWITCH
COMMAND
REGISTER
Programming and
PROGRAM VOLTAGE
ERASE VOLTAGE
SWITCH
SWITCH
Y-DECODER
X-DECODER
1
using a two write cycle scheme. Address and Data are
latched to free the I/O bus and address bus during the
write operation.
The CAT28F010 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.
Commercial, Industrial and Automotive
Temperature Ranges
On-Chip Address and Data Latches
JEDEC Standard Pinouts:
–32-pin DIP
–32-pin PLCC
–32-pin TSOP (8 x 20)
100,000 Program/Erase Cycles
10 Year Data Retention
Electronic Signature
CE, OE LOGIC
LATCH
DATA
I/O BUFFERS
1,048,576 BIT
I/O 0 –I/O 7
Y-GATING
MEMORY
ARRAY
second source
Licensed Intel
SENSE
AMP
Doc. No. 25005-0A 2/98 F-1
5108 FHD F02

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CAT28F010 Summary of contents

Page 1

... Programming and Erase Voltage Stop Timer for Program/Erase DESCRIPTION The CAT28F010 is a high speed 128K x 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 0.5 second. ...

Page 2

... CAT28F010 PIN CONFIGURATION DIP Package ( PLCC Package ( N ...

Page 3

... Units 100K Cycles/Byte 10 Years 2000 Volts 100 mA Limits Min Max 2.0V for periods of less than 20ns CAT28F010 Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17 Units Conditions OUT +1V ...

Page 4

... CAT28F010 D.C. OPERATING CHARACTERISTICS V = +5V 10%, unless otherwise specified. CC Symbol Parameter I Input Leakage Current LI I Output Leakage Current Standby Current CMOS SB1 Standby Current TTL SB2 Active Read Current CC1 CC ( Programming Current CC2 CC ( Erase Current CC3 ...

Page 5

... Figure 2. Highspeed A.C. Testing Input/Output 3.0 V INPUT PULSE LEVELS 0.0 V 5108 FHD F03 Testing Load Circuit (example) DEVICE UNDER TEST 5108 FHD F04 5 CAT28F010 Limits Min Max. Unit 4.5 5.5 0 6.5 12.6 (7) (7) 28F010-12 Unit 120 ns 90 120 ns 90 120 ...

Page 6

... CAT28F010 A.C. CHARACTERISTICS, Read Operation V = +5V 10%, unless otherwise specified. CC \JEDEC Standard Symbol Symbol Parameter t t Write Cycle Time AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH Data Hold Time WHDX DH CE Setup Time ...

Page 7

... Read X 90H Read X 20H Write A A0H Read IN X 40H Write X C0H Read X FFH Write , PPL PPH 7 CAT28F010 I/O Notes D OUT High-Z High-Z 31H 12V B4H 12V See Command Table IN D During Write Cycle IN D During Write Cycle ...

Page 8

... A Read cycle from address 0001H retrieves the binary code for the device on outputs I/O 28F010 Code = 1011 0100 (B4H) Standby Mode With logic-high level, the CAT28F010 is placed standby mode where most of the device circuitry is disabled, thereby substantially reducing power con- sumption ...

Page 9

... ERASE VERIFY COMMAND COMMAND WHWH2 DATA IN DATA IN = 20H = A0H 9 CAT28F010 to I ERASE V CC POWER-DOWN/ VERIFICATION STANDBY EHQZ t WHGL OLZ VALID t LZ DATA OUT ...

Page 10

... CAT28F010 (1) Figure 5. Chip Erase Algorithm START ERASURE APPLY V PPH PROGRAM ALL BYTES TO 00H INITIALIZE ADDRESS INITIALIZE PLSCNT = 0 WRITE ERASE SETUP COMMAND WRITE ERASE COMMAND TIME OUT 10ms WRITE ERASE VERIFY COMMAND TIME OUT 6 s INCREMENT ADDRESS READ DATA FROM DEVICE DATA = ...

Page 11

... DATA VERIFY PROGRAMMING COMMAND WHWH1 DATA IN DATA IN = C0H 11 CAT28F010 PROGRAM V CC POWER-DOWN/ VERIFICATION STANDBY EHQZ WHGL OLZ VALID t LZ DATA OUT t CE 28F010 F08 ...

Page 12

... CAT28F010 Figure 7. Programming Algorithm START PROGRAMMING APPLY V PPH INITIALIZE ADDRESS PLSCNT = 0 WRITE SETUP PROG. COMMAND WRITE PROG. CMD ADDR AND DATA TIME OUT 10 s WRITE PROGRAM VERIFY COMMAND TIME OUT 6 s READ DATA FROM DEVICE VERIFY DATA ? YES LAST NO INCREMENT ADDRESS? ...

Page 13

... In other words, V may power up in any order. Additionally V hardwired to V any power up/down cycling. The internal command register of the CAT28F010 is reset to the Read Mode on power up. POWER SUPPLY DECOUPLING To reduce the effect of transient power supply voltage spikes good practice to use a 0.1 F ceramic ...

Page 14

... CAT Product Number Optional Company ID * -40˚ to +125˚ is available upon request. Note: (1) The device used in the above example is a CAT28F010NI-90T(PLCC, Industrial Temperature access time, Tape & Reel). Doc. No. 25005-0A 2/98 F-1 28F010-70 28F010-90 Min. Max Min. Max Min. Max. Unit 70 90 ...

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