cav24c02 ON Semiconductor, cav24c02 Datasheet

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cav24c02

Manufacturer Part Number
cav24c02
Description
2-kb, 4-kb, 8-kb, And 16-kb I2c Cmos Serial Eeprom
Manufacturer
ON Semiconductor
Datasheet

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CAV24C02, CAV24C04,
CAV24C08, CAV24C16
2-Kb, 4-Kb, 8-Kb and 16-Kb
I
Description
respectively CMOS Serial EEPROM devices organized internally as
8/16/32/64 and 128 pages respectively of 16 bytes each. All devices
support both the Standard (100 kHz) as well as Fast (400 kHz) I
protocol.
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
CAV24C02, four CAV24C04, two CAV24C08 and one CAV24C16
device on the same bus.
Features
© Semiconductor Components Industries, LLC, 2011
April, 2011 − Rev. 1
2
The CAV24C02/04/08/16 are 2−Kb, 4−Kb, 8−Kb and 16−Kb
Data is written by providing a starting address, then loading 1 to 16
External address pins make it possible to address up to eight
and Change Control
(SCL and SDA)
Compliant
Automotive Temperature Grade 1 (−40°C to +125°C)
Supports Standard and Fast I
2.5 V to 5.5 V Supply Voltage Range
16−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
CAV Prefix for Automotive and Other Applications Requiring Site
Schmitt Triggers and Noise Suppression Filters on I
Low power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
C CMOS Serial EEPROM
A
2
, A
1
SCL
, A
WP
0
Figure 1. Functional Symbol
CAV24Cxx
V
V
CC
SS
2
C Protocol
SDA
2
C Bus Inputs
1
2
C
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
NC /
NC NC
NC
16 / 08 / 04 / 02
A0, A1, A2
Pin Name
/
/
CAV24C__
SDA
SCL
V
V
WP
CASE 948AL
NC
NC NC
A
CC
SS
TSSOP−8
Y SUFFIX
2
ORDERING INFORMATION
/
/
/
PIN CONFIGURATIONS
A
A
SOIC (W), TSSOP (Y)
1
2
http://onsemi.com
PIN FUNCTION
/
/
/
V
A
A
A
SS
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
No Connect
0
1
2
(Top View)
Publication Order Number:
1
2
3
4
Function
CASE 751BD
W SUFFIX
SOIC−8
8
7
6
5
CAV24C02/D
V
WP
SCL
SDA
CC

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cav24c02 Summary of contents

Page 1

... Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. External address pins make it possible to address up to eight CAV24C02, four CAV24C04, two CAV24C08 and one CAV24C16 device on the same bus. Features • ...

Page 2

Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Storage Temperature Voltage on any pin with respect to Ground (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is ...

Page 3

Table 5. A.C. CHARACTERISTICS (Note 2 5 −40°C to +125°C, unless otherwise specified Symbol F Clock Frequency SCL t START Condition Hold Time HD:STA t Low Period of SCL Clock ...

Page 4

... CC trigger level. This bi−directional POR feature protects the device against ‘brown−out’ failure following a temporary loss of power. *For common features, the CAV24C02/04/08/16 will be referred to as CAV24Cxx. Pin Description SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master. ...

Page 5

... Figure 3. Slave Address Bits 1 8 ACK DELAY ( Figure 4. Acknowledge Timing t t HIGH R t LOW LOW t HD:DAT t SU:DAT Figure 5. Bus Timing http://onsemi.com 5 STOP CONDITION CAV24C02 CAV24C04 CAV24C08 CAV24C16 BUS RELEASE DELAY (RECEIVER) 9 ACK SETUP ( SU:DAT t SU:STO t BUF ...

Page 6

... CAV24Cxx. After receiving another acknowledge from the Slave, the Master transmits the data byte to be written into the addressed memory location. The CAV24Cxx device will acknowledge the data byte and the Master generates the STOP condition, at which time the device begins its internal Write cycle to nonvolatile memory (Figure 6) ...

Page 7

SCL th SDA 8 Bit Byte n S BUS ACTIVITY SLAVE R MASTER ADDRESS SLAVE ADDRESS BYTE 1 SCL a 7 SDA WP ACK t WR STOP ...

Page 8

... CAV24Cxx will continue transmitting data residing at subsequent locations until the Master responds with a NoACK, followed by a STOP (Figure 12). In contrast to Page Write, during Sequential Read the address count will automatically increment to and then wrap−around at end of memory (rather than end of page SLAVE ...

Page 9

PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O SYMBOL ...

Page 10

E1 e TOP VIEW SIDE VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O SYMBOL MIN A A1 0.05 A2 ...

Page 11

... Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 11 − Tape & Reel (Note 13) T: Tape & Reel G: NiPdAu 3: 3000 Units / Reel ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CAV24C02/D ...

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