CD4071 Intersil Corporation, CD4071 Datasheet
CD4071
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CD4071 Summary of contents
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... Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Description CD4071BMS, CD4072BMS and CD4075BMS OR gates pro- vide the system designer with direct implementation of the positive-logic OR function and supplement the existing fam- ily of CMOS gates. ...
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... CD4071BMS, CD4072BMS, CD4075BMS Functional Diagram VDD VSS CD4071BMS VDD VSS CD4072BMS VDD ...
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... Specifications CD4071BMS, CD4072BMS, CD4075BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input Operating Temperature Range . . . . . . . . . . . . . . . . -55 Package Types Storage Temperature Range (TSTG -65 Lead Temperature (During Soldering +265 At Distance 1/16 1/32 Inch (1 ...
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... Specifications CD4071BMS, CD4072BMS, CD4075BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTES 1, 2) Propagation Delay TPHL VDD = 5V, VIN = VDD or GND TPLH Transition Time TTHL VDD = 5V, VIN = VDD or GND TTLH NOTES 50pF 200K, Input TR, TF < 20ns -55 C and +125 C limits guaranteed, 100% testing being implemented ...
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... Specifications CD4071BMS, CD4072BMS, CD4075BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Transition Time TTHL VDD = 10V TTLH VDD = 15V Input Capacitance CIN Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics 50pF 200K, Input TR, TF < ...
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... Specifications CD4071BMS, CD4072BMS, CD4075BMS TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 CONFORMANCE GROUP METHOD Group B Subgroup B-5 Sample 5005 Subgroup B-6 Sample 5005 Group D Sample 5005 NOTE Parameteric, 3% Functional; Cumulative for Static 1 and 2. MIL-STD-883 CONFORMANCE GROUPS METHOD Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS ...
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... CD4071BMS, CD4072BMS, CD4075BMS VDD ( (5,9, 12) n VSS FIGURE 1. SCHEMATIC DIAGRAM FOR CD4071BMS ( IDENTICAL GATES ( (5, 9, 12) FIGURE 2. LOGIC DIAGRAM FOR CD4071BMS ( IDENTICAL GATES) ** INV.1 VDD (12) n VSS * ** 3 (11) INV (9) INV ...
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... CD4071BMS, CD4072BMS, CD4075BMS (5, 13 (4, 12 (3, 11) FIGURE 5. SCHEMATIC DIAGRAM FOR CD4075BMS ( IDENTICAL GATES (3, 11 (4, 12 (5, 13) FIGURE 6. LOGIC DIAGRAM FOR CD4075BMS ( IDENTICAL GATES) Typical Performance Characteristics 20 AMBIENT TEMPERATURE ( +25 A SUPPLY VOLTAGE (VDD) = 15V 15 10V ...
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... CD4071BMS, CD4072BMS, CD4075BMS Typical Performance Characteristics AMBIENT TEMPERATURE ( + GATE-TO-SOURCE VOLTAGE (VGS) = 15V 10V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 9. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 o AMBIENT TEMPERATURE ( + GATE-TO-SOURCE VOLTAGE (VGS) = -5V ...
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... CD4071BMS, CD4072BMS, CD4075BMS Chip Dimensions and Pad Layouts CD4071BMS METALLIZATION: Thickness: 11k PASSIVATION: 10.4kÅ - 15.6k BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. ...