cdp68hc68p1 Intersil Corporation, cdp68hc68p1 Datasheet
cdp68hc68p1
Available stocks
Related parts for cdp68hc68p1
cdp68hc68p1 Summary of contents
Page 1
... Data Sheet CMOS Serial 8-Bit Input/Output Port The CDP68HC68P1 is a serially addressed 8-bit Input/Output port that allows byte or individual bit control. It consists of three registers, an output buffer and control logic. Data is shifted in and out of the device via shift register that utilizes the SPI (Serial Peripheral Interface) bus. The I/O port ...
Page 2
... CDP68HC68P1 SHIFT REGISTER CONTROL LOGIC COMPARATOR DIRECTION REGISTER INPUT/OUTPUT FIGURE 1. SINGLE PORT I/O BLOCK DIAGRAM CHIP CE ENABLE CDP68HC68P1 MOSI DATA IN MISO CLOCK SCK FIGURE 2. SINGLE PORT I/O SCK - Serial clock input. This input causes serial data to be latched from the MOSI input and shifted out on the MISO to V ...
Page 3
... Input Capacitance NOTES Typical values are for and nominal Outputs open circuited; cycle time = Min CDP68HC68P1 Thermal Information Thermal Resistance (Typical, Note 2) PDIP Package . . . . . . . . . . . . . . . . . . . +0.5V DD SOIC Package . . . . . . . . . . . . . . . . . . . Device Dissipation Per Output Transistor . . . . . . . . . . . . . . .100mW T = Full Package Temperature Range (All Package Types) ...
Page 4
... Data In to Clock Set-Up Time Data In after Clock Hold Time Clock to Data Propagation Delay Chip Disable to Output High Z Output Rise Time Output Fall Time Clock to Data Out Archive Clock Recovery Time 4 CDP68HC68P1 - ±10%, Unless Otherwise Specified. A ...
Page 5
... OR MSB MISO NOTE: CPOL and CPHA are bits in the CDP68HC05C4B and CDP68HC05C16B MCU control register and determine inactive clock polarity and phase. CPHA must always equal 1. FIGURE 5. DATA TRANSFERS UTILIZING CLOCK INPUT 5 CDP68HC68P1 C07 C06 COMPARE FLAG C05 C04 C00 t DVCV ...
Page 6
... DON’T CARE Z = HIGH IMPEDANCE * = COMPARE FLAG 6 CDP68HC68P1 programmed via C01 and C00 (CM1, CM0) of the Address Byte. As shown in Table 1, the values for CM1 and CM0 will sense one of four separate conditions. The compare flag is set to one when the programmed condition is satisfied ...
Page 7
... MOSI SCK CDP68HC68P1 C04 (R/W) - Read/Write. Low when data transferred from the SPI I/O to the CPU (read) and high when the I/O is receiving data from the CPU (write). C03 (DF1), C02 (DF0) - Data Format Bits. These have meaning only when R/W is high. During a write operation, DF1 and DF0 control how the byte following the control word is interpreted ...
Page 8
... B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 8 CDP68HC68P1 E16.3 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE SYMBOL E A2 ...
Page 9
... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 CDP68HC68P1 M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE ...