cdp68hc68t1 Intersil Corporation, cdp68hc68t1 Datasheet

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cdp68hc68t1

Manufacturer Part Number
cdp68hc68t1
Description
Cmos Serial Real-time Clock With Ram And Power Sense/control
Manufacturer
Intersil Corporation
Datasheet

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CMOS Serial Real-Time Clock With RAM
and Power Sense/Control
The CDP68HC68T1 Real-Time Clock provides a
time/calendar function, a 32 byte static RAM, and a 3 wire
Serial Peripheral Interface (SPI Bus). The primary function of
the clock is to divide down a frequency input that can be
supplied by the on-board oscillator in conjunction with an
external crystal or by an external clock source. The internal
oscillator can operate with a 32kHz, 1MHz, 2MHz, or 4MHz
crystal. An external clock source with a 32kHz, 1MHz, 2MHz,
4MHz, 50Hz or 60Hz frequency can be used to drive the
CDP68HC68T1. The time registers hold seconds, minutes,
and hours, while the calendar registers hold day-of-week,
date, month, and year information. The data is stored in BCD
format. In addition, 12 or 24 hour operation can be selected.
In 12 hour mode, an AM/PM indicator is provided. The T1
has a programmable output which can provide one of seven
outputs for use elsewhere in the system.
Computer handshaking is controlled with a “wired-OR” interrupt
output. The interrupt can be programmed to provide a signal as
the result of:
Pinouts
1. An alarm programmed to occur at a predetermined
2. One of 15 periodic interrupts ranging from sub-second to
3. A power fail detect. The PSE output and the V
combination of seconds, minutes, and hours.
once per day frequency.
used for external power control. The CPUR output is
available to reset the processor under power-down
conditions. CPUR is enabled under software control and
can also be activated via the CDP68HC68T1’s watchdog. If
enabled, the watchdog requires a periodic toggle of the CE
pin without a serial transfer.
CLKOUT
CPUR
MOSI
MISO
SCK
V
INT
CE
SS
1
2
3
4
5
6
7
8
(16 LD PDIP, SOIC)
CDP68HC68T1
TOP VIEW
®
1
Data Sheet
16
15
14
13
12
11
10
9
V
XTAL OUT
XTAL IN
V
V
LINE
POR
PSE
DD
BATT
SYS
SYS
input are
1-888-INTERSIL or 1-888-468-3774
Copyright Harris Corporation 1997. Copyright Intersil Americas Inc. 2001, 2004-2007. All Rights Reserved
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• SPI (Serial Peripheral Interface)
• Full Clock Features
• 32 Wordx8-Bit RAM
• Seconds, Minutes, Hours Alarm
• Automatic Power Loss Detection
• Low Minimum Standby (Timekeeping) Voltage . . . . . 2.2V
• Selectable Crystal or 50/60Hz Line Input
• Buffered Clock Output
• Battery Input Pin that Powers Oscillator and also
• Three Independent Interrupt Modes
• Pb-Free Available (RoHS Compliant)
- Seconds, Minutes, Hours (12/24, AM/PM), Day of
Connects to V
- Alarm
- Periodic
- Power-Down Sense
Week, Date, Month, Year (0 to 99), Automatic Leap Year
October 29, 2007
All other trademarks mentioned are the property of their respective owners.
|
CLK OUT
Intersil (and design) is a registered trademark of Intersil Americas Inc.
CPUR
MOSI
MISO
SCK
PSE
V
INT
DD
NC
CE
SS
Pin When Power Fails
10
1
2
3
4
5
6
7
8
9
CDP68HC68T1
(20 LD SOIC)
TOP VIEW
CDP68HC68T1
20
19
18
17
16
15
14
13
12
11
VDD
XTAL OUT
XTAL IN
NC
V
V
NC
NC
LINE
POR
BATT
SYS
FN1547.8

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cdp68hc68t1 Summary of contents

Page 1

... The CPUR output is available to reset the processor under power-down conditions. CPUR is enabled under software control and can also be activated via the CDP68HC68T1’s watchdog. If enabled, the watchdog requires a periodic toggle of the CE pin without a serial transfer. Pinouts ...

Page 2

... CDP68HC68T1M2* HC68T1M2 CDP68HC68T1M2Z* (Note) HC68T1M2Z *Add “96” suffix for tape and reel. Please refer to TB347 for details on reel specifications. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. ...

Page 3

... Current Drain Per Input Pin (Excluding V DD Current Drain Per Output Pin 40mA Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0V to +6.0V Standby (Timekeeping) Voltage . . . . . . . . . . . . . . . . . +2.2V to +6.0V Temperature Range CDP68HC68T1E (PDIP Package .-40°C to +85°C CDP68HC68T1M/M2 (SOIC Packages .-40°C to +85°C Input Voltage Input High . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(0 Input Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Clock Frequency ( +3.0V to +6.0V SCK CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time ...

Page 4

... DC V SYMBOL MIN t 200 EVCV t 250 CVEX t 400 WH t 400 WL t 200 DVCV t - CVDV t - EXQZ 200 CVDX t - CVQX t 200 REC CDP68HC68T1 TYP MIN (Note 2) MAX 0.025 0.015 - 0.08 0.15 - 0.15 0.25 - 0.3 0 1.0 100 75 = -40°C to +85°C A LIMITS (ALL TYPES ...

Page 5

Functional Block Diagram CE LINE 50/60Hz XTAL IN OSCILLATOR PRESCALE XTAL OUT V BATT PRESCALE SELECT CLOCK OUT CONTROL REGISTER INT CLOCK AND V INTERRUPT DD INT CONTROL LOGIC V SS REGISTER LINE V POWER SYS INT STATUS SENSE REGISTER ...

Page 6

... Most significant Bit, D7, is “0” for 24 hours, and “1” for 12 hour mode. Data Bit D5 is “1” for PM and ‘0” for hour mode. 6. Alarm hours. Data Bit D5 is “1” for PM and “0” for hour mode. Data Bits D7 and D6 are DON’T CARE. 6 CDP68HC68T1 $00 32 ...

Page 7

... Programmers Model - Clock Registers HEX ADDRESS RAM DATA BYTE NOTE Don’t care writes when read. 7 CDP68HC68T1 WRITE/READ REGISTERS DB7 DB0 TENS UNITS TENS UNITS PM/ UNITS TENS ...

Page 8

... The calendar counters consist of day (day of week), date (day of month), month and 8 CDP68HC68T1 years information. Data in the counters is in BCD format. The hours counter utilizes BCD for hour data plus bits for 12/24 hour and AM/PM. The seven time counters are accessed serially at addresses 20H through 26H ...

Page 9

... INT CPU CDP68HC05C16B POWER-UP PSE POWER SENSE OR ALARM CPUR CIRCUIT CLK OUT PERIODIC INTERRUPT SIGNAL INT MISO SERIAL INTERFACE MOSI REAL-TIME CLOCK CDP68HC68T1 BY INTERRUPT SIGNAL (See Figure 4) (See Figures 5 and 6) FN1547.8 October 29, 2007 ...

Page 10

... The CDP68HC68T1 has an on-board 150kΩ resistor that is switched in series with its internal inverter when 32kHz is selected via the Clock Control Register. Note: When first powered up the series resistor is not part of the oscillator circuit. (The CDP68HC68T1 sets up for a 4MHz oscillator). rises above the V voltage after V BATT is a logic high) ...

Page 11

... PSE pin will return high and the Clock Output will be enabled. The CPUR output pin will also return high. The logic level present at this pin at the end of POR determines the CDP68HC68T1’s operating mode. V BATT The oscillator power source. The positive terminal of the battery should be connected to this pin ...

Page 12

... NOTE: All bits are reset by power-on reset VALUE CDP68HC68T1 Periodic Select The value in these 4 bits will select the frequency of the periodic output. (See Table 3 XTAL XTAL 50Hz SEL SEL 1 0 60Hz POWER ...

Page 13

... Clock Interrupt A periodic interrupt will set this bit high. All bits are reset by a power-on reset except the “FIRST- TIME UP” which is set. All bits except the power-sense bit are reset after a read of this register. 13 CDP68HC68T1 TEST FIRST INTERRUPT ...

Page 14

... Functional Description The Serial Peripheral Interface (SPI) utilized by the CDP68HC68T1 is a serial synchronous bus for address and data transfers. The clock, which is generated by the microcomputer is active only during address and data transfers. In systems using the CDP68HC05C4 or CDP68HC05D2, the inactive clock polarity is determined by the CPOL bit in the microcomputer’ ...

Page 15

... NOTE: SCK can be either polarity. FIGURE 10. READ/WRITE DATA TRANSFER WAVEFORMS Watchdog Reset (See Figure 11) When watchdog operation is selected, CE must be toggled periodically or a CPU reset will be outputted. SERVICE TIME CE SCK CPUR FIGURE 11. WATCHDOG OPERATION WAVEFORMS 15 CDP68HC68T1 ...

Page 16

... SCK WRITE MOSI ADDRESS BYTE MOSI ADDRESS BYTE READ MISO DATA BYTE W/R ADDRESS DATA BYTE +1 DATA BYTE + (n-1) FIGURE 13. MULTIPLE-BYTE TRANSFER WAVEFORMS 16 CDP68HC68T1 WRITE DATA READ DATA DATA BYTE DATA BYTE DATA BYTE DATA BYTE DATA BYTE DATA BYTE FN1547.8 October 29, 2007 ...

Page 17

... NOTE: Example of a system in which power is always on. Clock circuit driven by line input frequency. FIGURE 16. POWER-ON ALWAYS SYSTEM DIAGRAM 17 CDP68HC68T1 FIGURE 14. WRITE-CYCLE TIMING WAVEFORMS FIGURE 15. READ-CYCLE TIMING WAVEFORMS V POR DD INT V SYS V DD LINE CDP68HC68T1 V BATT CPUR CE SCK MOSI MISO XTAL ...

Page 18

... NOTE: Example of a system in which the power is controlled by an external source. The LINE input pin can sense when the switch opens by use of the POWER-SENSE INTERRUPT. The CDP68HC68T1 crystal drives the clock input to the CPU using the CLK OUT pin. On power down when V < ...

Page 19

... System Diagrams (Continued) AC REGULATOR LINE 0.1 R CHARGE 0.047 1k 20k RTC V DD FIGURE 18. EXAMPLE OF A SYSTEM WITH A BATTERY BACKUP 19 CDP68HC68T1 NC 100k POR SYS V BATT PSE XTAL CPUR V DD LINE INT CLK OUT CE SPI (EPS) ENABLED POWER SUPPLY V DD RESET CDP68HC05C4B IRQ ...

Page 20

... Also, the CMOS CPU is not powered down with the system V , but is held in a low power reset mode during power down. When restoring power the CDP68HC68T1 DD will enable the CLK OUT pin and set the PSE and CPUR high. ...

Page 21

... B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 21 CDP68HC68T1 E16.3 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE SYMBOL E A2 ...

Page 22

... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 22 CDP68HC68T1 M16.3 (JEDEC MS-013-AA ISSUE C) 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE M B ...

Page 23

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 23 CDP68HC68T1 M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE ...

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