clc5612 National Semiconductor Corporation, clc5612 Datasheet

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clc5612

Manufacturer Part Number
clc5612
Description
Dual, High Output, Programmable Gain Buffer
Manufacturer
National Semiconductor Corporation
Datasheet

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© 2001 National Semiconductor Corporation
CLC5612
Dual, High Output, Programmable Gain Buffer
General Description
The CLC5612 is a dual, low cost, high speed (90MHz) buffer
which features user programmable gains of +2, +1, and
−1V/V. The CLC5612 also has a new output stage that
delivers high output drive current (130mA), but consumes
minimal quiescent supply current (1.5mA/ch) from a single
5V supply. Its current feedback architecture, fabricated in an
advanced
consistent performance over a wide range of gains and
signal levels, and has a linear phase response up to one half
of the −3dB frequency.
The CLC5612 offers 0.1dB gain flatness to 18MHz and
differential gain and phase errors of 0.15% and 0.02˚. These
features are ideal for professional and consumer video
applications.
The CLC5612 offers superior dynamic performance with a
90MHz small signal bandwidth, 290V/µs slew rate and 6.2ns
rise/fall times (2V
power, high output current drive, and high speed
performance make the CLC5612 well suited for many
battery powered personal communication/computing sys-
tems.
The ability to drive low impedance, highly capacitive loads,
makes the CLC5612 ideal for single ended cable
applications. It also drives low impedance loads with
minimum distortion. The CLC5612 will drive a 100
with only −74/−86dBc second/third harmonic distortion (A
+2, V
conditions, it produces only -70/-67dBc second/third
harmonic distortion. It is also optimized for driving high
currents into single-ended transformers and coils.
When driving the input of high resolution A/D converters, the
CLC5612 provides excellent −87/−93dBc second/third
harmonic distortion (A
and fast settling time.
Features
n 130mA output current
Connection Diagram
OUT
= 2V
complementary
PP
, f = 1MHz). With a 25 load, and the same
step
). The combination of low quiescent
V
= +2, V
bipolar
OUT
, f = 1MHz, R
process,
DS015001
maintains
L
= 1k )
load
V
DIP & SOIC
=
Pinout
n 0.15%, 0.02˚ differential gain, phase
n 1.5mA/ch supply current
n 90MHz bandwidth (A
n −87/−93dBc HD2/HD3 (1MHz)
n 17ns settling to 0.05%
n 290V/µs slew rate
n Stable for capacitive loads up to 1000pf
n Single 5V to
Applications
n Video line driver
n Coaxial cable driver
n Twisted pair driver
n Transformer/coil driver
n High capacitive load driver
n Portable/battery powered applications
n A/D driver
DS015001-3
Maximum Output Voltage vs. R
±
5V supplies
V
= +2)
DS015001-1
January 2001
L
www.national.com

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clc5612 Summary of contents

Page 1

... CLC5612 Dual, High Output, Programmable Gain Buffer General Description The CLC5612 is a dual, low cost, high speed (90MHz) buffer which features user programmable gains of +2, +1, and −1V/V. The CLC5612 also has a new output stage that delivers high output drive current (130mA), but consumes minimal quiescent supply current (1 ...

Page 2

... Differential Line Driver with Load Impedance Conversion Ordering Information Package 8-pin plastic DIP 8-pin plastic SOIC www.national.com Temperature Range Part Number Industrial −40˚C to +85˚C CLC5612IN −40˚C to +85˚C CLC5612IM CLC5612IMX 2 DS015001-2 Package NSC Marking Drawing CLC5612IN N08E CLC5612IM M08A CLC5612IM ...

Page 3

... Power Supply Rejection Ratio (Note 1) Output Current (see (Note 4)) Common-Mode Input Voltage Maximum Junction Temperature Storage Temperature Range Lead Temperature (soldering 10 sec) ± 7V +14V + (V /2), R tied unless specified Conditions CLC5612IN < 200MHz 0. < ...

Page 4

... Harmonic Distortion Equivalent Input Noise www.national.com (Continued /2), R tied unless specified Conditions 100 100 Conditions CLC5612IN < 200MHz 1. < 30MHz 1. < 30MHz 1. NTSC 150 L NTSC, R ...

Page 5

Electrical Characteristics ± + 100 , V = 5V, unless specified Symbol Parameter Distortion And Noise Response Voltage ( Non-Inverting Current (i bn Inverting Current ( Crosstalk ...

Page 6

Typical Performance Characteristics V , unless specified) (Continued) CM Gain Flatness & Linear Phase Gain Phase Frequency (MHz) Frequency Response ...

Page 7

Typical Performance Characteristics V , unless specified) (Continued) CM 2nd & 3rd Harmonic Distortion - 3rd - -70 2nd -80 -90 3rd R = 100 L -100 ...

Page 8

Typical Performance Characteristics V , unless specified) (Continued & V vs. Temperature BN IO 1 -0.5 -1 -1.5 -60 -40 - Temperature ( C) Frequency Response vs. R ...

Page 9

Typical Performance Characteristics V , unless specified) (Continued) CM Frequency Response vs − 10M Frequency (Hz) Differential Gain & ...

Page 10

Typical Performance Characteristics V , unless specified) (Continued) CM 2nd & 3rd Harmonic Distortion vs. Frequency -50 3rd, 10MHz -60 -70 2nd, 10MHz -80 2nd, 1MHz -90 3rd, 1MHz -100 -110 Output Amplitude (V ...

Page 11

... CLC5612 Design Information ± 5V Electrical Closed Loop Gain Selection The CLC5612 is a current feedback op amp with R on chip (in the package). Select from three closed loop gains without using any external gain or feedback resistors. Implement gains of +2, +1, and −1V/V by connecting pins 2 and 3 (or 5 and 6) as described in the chart below. ...

Page 12

... Application Division (Continued) Operating from a single +5V supply, the Common Mode Input Range (CMIR) of the CLC5612 is typically +0.8V to +4.2V. The typical output range with R +4.0V. For single supply DC coupled operation, keep input signal levels above 0.8V DC. For input signals that drop below 0.8V DC, AC coupling and level shifting the signal are recommended ...

Page 13

... Application Division (Continued) Dual Supply Operation The CLC5612 on dual supplies as well as single supplies. The non-inverting and inverting configurations are shown in Figure 7 , Figure 8 , and Figure FIGURE 7. Dual Supply FIGURE 8. Dual Supply ...

Page 14

... Calculate the total RMS power: P The maximum power that the DIP and SOIC, packages can dissipate at a given temperature is illustrated in Figure 12 . The power derating curve for any CLC5612 package can be derived by utilizing the following equation: where T amb ...

Page 15

... Special Evaluation Board Considerations for the CLC5612 To optimize off-isolation of the CLC5612, cut the R both the CLC730038 and the CLC730036 evaluation boards. This cut minimizes capacitive feedthrough between the input and the ouptut. Figure 13 shows where to cut both evaluation boards for improved off-isolation ...

Page 16

... Application Circuits Single Supply Cable Driver Figure 14 below shows the CLC5612 driving 10m of 75 coaxial cable. The CLC5612 is set for a gain of +2V/V to compensate for the divide-by-two voltage drop at V response after 10m of cable is illustrated in Figure 15 . 10m of 75 Coaxial Cable ...

Page 17

... Application Division (Continued) Differential Input/Differential Output Amplifier Figure 17 below illustrates a differential input/differential output configuration. The bypass capacitors are the only external components required CLC5612 6.8 F 0.1 F +5V FIGURE 17. Differential Input/Differential Output Amplifier 17 -5V 0 out V 1 out V 1 – ...

Page 18

Physical Dimensions National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise ...

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