COM20019ILJP SMSC, COM20019ILJP Datasheet
COM20019ILJP
Specifications of COM20019ILJP
Related parts for COM20019ILJP
COM20019ILJP Summary of contents
Page 1
... COM20019I 3VLJP for 28 pin PLCC * package COM20019I 3V-DZD for 28 pin PLCC * Lead-Free RoHS Compliant package COM20019I 3V-HT for 48 pin TQFP Lead-Free RoHS Compliant package * TQFP package is recommended for new design SMSC COM20019I 3.3V Rev.C COM20019I 3.3V Rev.C Cost Competitive ARCNET (ANSI 878.1) ...
Page 2
... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“ ...
Page 3
... Access Speed.........................................................................................................................................37 6.4 SOFTWARE INTERFACE .............................................................................................................37 6.4.1 Selecting RAM Page Size.......................................................................................................................38 6.4.2 Transmit Sequence.................................................................................................................................39 6.4.3 Receive Sequence..................................................................................................................................40 6.5 COMMAND CHAINING.................................................................................................................. 41 6.5.1 Transmit Command Chaining .................................................................................................................42 6.5.2 Receive Command Chaining ..................................................................................................................42 6.6 RESET DETAILS ........................................................................................................................... 43 SMSC COM20019I 3.3V Rev.C TABLE OF CONTENTS Page 3 DATASHEET Rev. 11-07-08 ...
Page 4
... Pin TQFP Package Outline and Parameters ............................................................................ 65 Chapter 10 Appendix A...................................................................................................................... 66 10.1 NOSYNC Bit................................................................................................................................... 66 10.2 EF Bit.............................................................................................................................................. 66 Chapter 11 Appendix B ...................................................................................................................... 69 Chapter 12 Appendix C...................................................................................................................... 70 12.1 Software Identification of the COM20019I 3V Rev B and Rev C................................................... 70 Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 4 DATASHEET SMSC COM20019I 3.3V Rev.C ...
Page 5
... Table 6.5 - Command Register.....................................................................................................................................31 Table 6.6 - Address Pointer High Register ....................................................................................................................32 Table 6.7 - Address Pointer Low Register.....................................................................................................................32 Table 6.8 - Sub Address Register .................................................................................................................................33 Table 6.9 - Configuration Register ................................................................................................................................33 Table 6.10 - Setup 1 Register .......................................................................................................................................34 Table 6.11 - Setup 2 Register .......................................................................................................................................35 SMSC COM20019I 3.3V Rev.C Page 5 DATASHEET Rev. 11-07-08 ...
Page 6
... Chapter 1 SMSC's COM20019I member of the family of Embedded ARCNET Controllers from Standard Microsystems Corporation. The device is a general purpose communications controller for networking microcontrollers and intelligent peripherals in industrial and embedded control environments using an ARCNET protocol engine. The flexible microcontroller and media interfaces, eight-page message support, and extended temperature range of the COM20019I 3V make it the only true network controller optimized for use in industrial and embedded applications ...
Page 7
... A1 2 A2/ALE 3 AD0 4 AD1 5 AD2 VSS Package: 28-Pin PLCC Packages: 24-Pin DIP or 28-Pin PLCC Ordering Information: COM20019 I P SMSC COM20019I 3.3V Rev.C Pin Configurations 24 VDD 23 nRD/nDS 25 22 nWR/DIR nWR/DIR 26 21 nCS 27 nRD/nDS 20 nINTR VDD 28 19 nRESET IN COM20019I 3V 18 nTXEN 1 A0/nMUX 17 RXIN ...
Page 8
... D3 7 VDD VSS Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM COM20020I 48 PIN TQFP NOTE: BUSTMG pin is only TQFP package Page 8 DATASHEET 36 nCS 35 VDD 34 nINTR 33 N/C 32 VDD 31 nRESET 30 VSS 29 nTXEN 28 RXIN 27 N/C 26 BUSTMG 25 nPULSE2 SMSC COM20019I 3.3V Rev.C ...
Page 9
... Select - 26 Read/Write Bus Timing Select SMSC COM20019I 3.3V Rev.C Description of Pin Functions SYMBOL I/O MICROCONTROLLER INTERFACE On a non-multiplexed mode, A0-A2 are address A0/nMUX IN input bits. (A0 is the LSB multiplexed A1 IN address/data bus, nMUX tied Low left open, and ALE is tied to the Address Latch Enable signal ...
Page 10
... Oscillation frequency range is from 10 MHz to XTAL2 OUT 20 MHz external TTL clock is used instead, it must be connected to XTAL1 with a 390ohm pull-up resistor, and XTAL2 should be left floating. +3.3 Volt power supply pins. VDD PWR Ground pins. VSS PWR Non-connection N/C Page 10 DATASHEET DESCRIPTION SMSC COM20019I 3.3V Rev.C ...
Page 11
... DID refers to the destination identification. - SOH refers to the start of header character; preceeds all data packets. * Reconfig timer is programmable via setup2 register bits 1, 0. Note - All time values are valid for 312.5 Kbps. SMSC COM20019I 3.3V Rev.C Power On Send Reconfigure Burst Read Node ID ...
Page 12
... ID. The COM20019I 3V starts network reconfiguration by sending an invitation to transmit first to itself and Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Protocol Description DATA RATE Div 312.5 Kbps 156.25 Kbps Page 12 DATASHEET TIMEOUT SCALING FACTOR (MULTIPLY BY SMSC COM20019I 3.3V Rev.C ...
Page 13
... The Idle Time is associated with a NETWORK RECONFIGURATION. Figure 3.1 illustrates that during a NETWORK RECONFIGURATION one node will continually transmit INVITATIONS TO TRANSMIT until it encounters an active node. All other nodes on the network must distinguish between this operation and an SMSC COM20019I 3.3V Rev.C Page 13 DATASHEET During NETWORK Rev ...
Page 14
... An ALERT BURST An ENQ (ENQuiry: ASCII code 85H) Two (repeated) DID (Destination ID) characters Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM ALERT EOT DID BURST ALERT ENQ DID BURST Page 14 DATASHEET DID DID SMSC COM20019I 3.3V Rev.C ...
Page 15
... An ACK (ACKnowledgement--ASCII code 86H) character 4.6.5 Negative Acknowledgements A Negative Acknowledgement is used as a negative response to FREE BUFFER ENQUIRIES and is sent by the following sequence: An ALERT BURST A NAK (Negative Acknowledgement--ASCII code 15H) character SMSC COM20019I 3.3V Rev.C DID DID COUNT data ALERT BURST ACK ...
Page 16
... Whenever the pointer is loaded for reads with a new value, data is immediately prefetched to prepare for the first read operation. Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM System Description Page 16 DATASHEET Once the type of bus is SMSC COM20019I 3.3V Rev.C ...
Page 17
... A15 RESET nRD nWR nINT1 8051 RXIN TXEN nPULSE1 nPULSE2 GND BACKPLANE CONFIGURATION FIGURE A Figure 5.1 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE SMSC COM20019I 3.3V Rev.C COM20022 AD0-AD2, D3-D7 A2/BALE RXIN nCS 75176B or nRESET nTXEN Equiv. nPULSE1 nRD/nDS nPULSE2 nWR/DIR ...
Page 18
... HYC9088 RXIN 12 N/C 11 5.6K nPULSE1 1/2W 5.6K nPULSE2 1/2W 17, 19 Traditional Hybrid 0.47 Configuration uF - *Valid for 2.5 Mbps only. uF FIGURE C Page 18 DATASHEET 75176B or Equiv. Differential Driver Configuration * Media Interface may be replaced with Figure 0.01 uF 1KV SMSC COM20019I 3.3V Rev.C ...
Page 19
... The BUSTMG pin (TQFP package only) is used to support this function used to Enable/Disable the High Speed CPU Read and Write function defined as: BUSTMG = 0, the High Speed CPU Read and SMSC COM20019I 3.3V Rev.C VALID VALID ...
Page 20
... Normal Speed CPU Read and Write High Speed CPU Read and Normal Speed CPU Write BUS TIMING MODE X High Speed CPU Read and Write 0 Normal Speed CPU Read and Write 1 High Speed CPU Read and Normal Speed CPU Write Page 20 DATASHEET SMSC COM20019I 3.3V Rev.C ...
Page 21
... ARCNET applications. (Refer to Note 5.1) The user may interface to the cable of choice in one of three ways: Note 5.1 Please refer to TN7-5 – Cabling Guidelines for the COM20020 ULANC, available from SMSC, for recommended cabling distance, termination, and node count for ARCNET nodes. 5.2.1 ...
Page 22
... Backplane Mode operation. The nPULSE2 pin should remain grounded at all times if an active high polarity is desired. Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM For typical single-ended backplane Page 22 DATASHEET coupled SMSC COM20019I 3.3V Rev.C ...
Page 23
... ADDRESS DECODING CIRCUITRY AD0-AD2, D3-D7 STATUS/ nINTR COMMAND REGISTER RESET nRESET LOGIC nRD/nDS nWR/DIR BUS ARBITRATION nCS CIRCUITRY Figure 5.5 SMSC COM20019I 3. RAM MICRO- SEQUENCER AND WORKING REGISTERS OSCILLATOR NODE ID RECONFIGURATION LOGIC TIMER - INTERNAL BLOCK DIAGRAM Page 23 DATASHEET ADDITIONAL REGISTERS nPULSE1 ...
Page 24
... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Table 5.1 - Typical Media NOMINAL ATTENUATION PER 1000 FT. IMPEDANCE 93Ω 75Ω 75Ω 150Ω 100Ω 105Ω Page 24 DATASHEET AT 5 MHZ 5.5dB 7.0dB 5.5dB 7.0dB 17.9dB 16.0dB SMSC COM20019I 3.3V Rev.C ...
Page 25
... FOUR MODE NAKS NEXT ID NXT ID7 NXT ID6 SETUP2 RBUS- X TMG Note*: (R/W) These bits can be Written or Read. For more information see Appendix C. SMSC COM20019I 3.3V Functional Description Table 6.1 - Read Register Summary READ X/TA POR TEST TOKEN RCV- EXC- ACT ...
Page 26
... ADDRESS PTR HIGH A1 A0 ADDRESS PTR LOW D1 D0 DATA SUBADR SUB- SUB- AD1 AD0 SUB- SUB- CONFIG- AD1 AD0 URATION TID1 TID0 TENTID NID1 NID0 NODEID SETUP1 CKP1 SLOW- ARB 0 0 TEST RCN- RCN- SETUP2 TM1 TM0 SMSC COM20019I 3.3V Rev.C ...
Page 27
... The COM20019I 3V Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and 6, are software compatible with previous SMSC ARCNET devices. In previous SMSC ARCNET devices the Extended Timeout status was provided in bits 5 and 6 of the Status Register. In the COM20019I 3V, the COM20020, the COM90C66, and the COM90C165, COM20020-5, COM20051 and COM20051+ these bits exist in and are controlled by the Configuration Register ...
Page 28
... The data rate may be slowed to 156.25Kbps and/or the arbitration speed may be slowed by a factor of two. The Setup 1 Register defaults to the value 0000 0000 upon hardware reset only. Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 28 DATASHEET Any SMSC COM20019I 3.3V Rev.C ...
Page 29
... BIT BIT NAME SYMBOL 7 Receiver RI Inhibited 6,5 (Reserved) 4 Power On Reset POR 3 Test TEST SMSC COM20019I 3.3V RCNTM0 TIME-OUT PERIOD 840 mS 1 420 mS* Table 6.3 - Status Register DESCRIPTION This bit, if high, indicates that the receiver is not enabled because either an "Enable Receive to Page fnn" command was never issued packet has been deposited into the RAM buffer page fnn as specified by the last " ...
Page 30
... Enquiry. This bit is cleared upon the "POR Clear Flags" command. Reading the Diagnostic Status Register does not clear this bit. This bit, when set, will cause an interrupt if the corresponding bit in the IMR is also set. Refer to the Improved Diagnostics section for further detail. Page 30 DATASHEET SMSC COM20019I 3.3V Rev.C ...
Page 31
... Page fnn 00fn n011 Enable Transmit from Page fnn SMSC COM20019I 3.3V DESCRIPTION This bit, if high, indicates that a response to a token whose DID matches the value in the Tentative ID Register has occurred. The second DID and the trailing zero's are not checked. Since ...
Page 32
... These bits are undefined. They must be 0. A10-A8 These bits hold the upper three address bits which provide addresses to RAM. Table 6.7 - Address Pointer Low Register SYMBOL DESCRIPTION A7-A0 These bits hold the lower 8 address bits which provide the addresses to RAM. Page 32 DATASHEET SMSC COM20019I 3.3V Rev.C ...
Page 33
... CCHEN This bit, if high, enables the Command Chaining operation of the device. Please refer to the Command Chaining section for further details. A low level on this bit ensures software compatibility with previous SMSC ARCNET devices. TXEN When low, this bit disables transmissions by keeping nPULSE1, nPULSE2 if in non-Backplane Mode, and nTXEN pin inactive ...
Page 34
... COM20019I 3V is not passing tokens. Defaults low. Page 34 DATASHEET Response Idle Time Reconfig Time (mS) (mS) Time (S) 9.548 10.496 13.44 4.774 5.248 13.44 2.387 2.624 13.44 0.597 0.656 6.72 Register Tentative I Node ID Setup 1 Next ID SMSC COM20019I 3.3V Rev.C ...
Page 35
... BIT NAME 7 Read Bus Timing Select 6,5,4 Reserved 3 Enhanced Functions 2 No Synchronous 1,0 Reconfiguration Timer 1, 0 SMSC COM20019I 3.3V SYMBOL DESCRIPTION CKP3,2,1 These bits are used to determine the data rate of the COM20019I 3V. The following table is for a 20 MHz crystal: CKP3 CKP2 CKP1 ...
Page 36
... I/O Address 04H D0-D7 Address Pointer Register I/O Address 02H High 11-Bit Counter Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Memory Data Bus 8 I/O Address 03H Low Memory Address Bus 11 Page 36 DATASHEET INTERNAL RAM SMSC COM20019I 3.3V Rev.C ...
Page 37
... For systems which do not require quick access time, the arbitration clock may be slowed down by setting bit 0 of the Setup1 Register equal to logic "1". Since the Slow Arbitration feature divides the input clock by two, the duty cycle of the input clock may be relaxed. 6.4 SOFTWARE INTERFACE SMSC COM20019I 3.3V SEQUENTIAL ACCESS OPERATION Page 37 DATASHEET The ...
Page 38
... Command Chaining only requires two pages for transmit and two for receive (in this case, a total of four 256 byte pages, leaving 1K free). The general rule which may be applied to determine where in RAM a page begins is as follows: Address = (nn x 512 256). Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 38 DATASHEET The SMSC COM20019I 3.3V Rev.C ...
Page 39
... A minimum value of 257 exists on a long packet so that the COUNT is expressible in eight bits. This leaves three exception packet lengths which do not fit into either a short or long packet; packet lengths of 254, 255, or 256 bytes. If packets of these SMSC COM20019I 3.3V FORMAT ADDRESS ...
Page 40
... Receive to Page fnn" command, which resets the RI bit to logic "0" and selects a new page in the RAM buffer. Again, the appropriate buffer size is specified in the "Define Configuration" Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 40 DATASHEET SMSC COM20019I 3.3V Rev.C ...
Page 41
... Through the use of a dual two-level FIFO, commands to be transmitted and received, as well as the status bits, are pipelined. In order for the COM20019I compatible with previous SMSC ARCNET device drivers, the device defaults to the non-chaining mode. In order to take advantage of the Command Chaining operation, the Command Chaining Mode must be enabled via a logic " ...
Page 42
... After reading the Status Register, the "Clear Receive Interrupt" command should be issued, thus resetting the TRI bit and clearing the interrupt. Note that only the "Clear Receive Interrupt" command will clear the Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 42 DATASHEET This SMSC COM20019I 3.3V Rev.C ...
Page 43
... Writing to and reading from an odd address location from the COM20019I 3V's address space causes the COM20019I 3V to determine the appropriate bus interface. When the COM20019I 3V is powered on the SMSC COM20019I 3.3V This pulse width is used by the internal digital filter, which XTL. ...
Page 44
... TXEN bit of the Configuration Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Reading the Diagnostic Status Register resets the MYRECON bit. Page 44 DATASHEET SMSC COM20019I 3.3V Rev.C ...
Page 45
... NODE ID already exists on the network. The software should periodically place values in the Tentative ID Register and monitor the New Next ID bit to maintain an updated network map. 6.9 OSCILLATOR The COM20019I 3V contains circuitry which, in conjunction with an external parallel resonant crystal or TTL clock, forms an oscillator. SMSC COM20019I 3.3V Page 45 DATASHEET Rev. 11-07-08 ...
Page 46
... The user may attach an external TTL clock, rather than a crystal, to the XTAL1 signal. In this case, a 390Ω pull-up resistor is required on XTAL1, while XTAL2 should be left unconnected. Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 46 DATASHEET SMSC COM20019I 3.3V Rev.C ...
Page 47
... Low Input Voltage 1 (All inputs except XTAL1) High Input Voltage 1 (All inputs except XTAL1) Low Input Voltage 2 (XTAL1) High Input Voltage 2 (XTAL1) Low Output Voltage 1 (nTXEN) High Output Voltage 1 (nTXEN) SMSC COM20019I 3.3V Operational Description SYMBOL MIN TYP MAX 0.8 V -0.3 IL1 V 2.0 5 ...
Page 48
... Page 48 DATASHEET UNIT COMMENT V I =8mA SINK V I =-4mA SOURCE V I =8mA SINK Open Drain Driver mA 312.5 Kbps All Outputs Open µA V =0.0V IN µA V < V < UNIT COMMENT pF pF Maximum Capacitive Load which can be supported by each output. SMSC COM20019I 3.3V Rev.C ...
Page 49
... Inputs are driven at 2.4V for logic "1" and 0.4 V for logic "0" except XTAL1 pin. Outputs are measured at 2.0V min. for logic "1" and 0.8V max. for logic "0". SMSC COM20019I 3.3V t 2.0V 0.8V 2.0V 50% 0.8V t Figure 7 MEASUREMENTS ...
Page 50
... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Timing Diagrams VALID DATA VALID t1 t2 t12 t11 t6 t13 t5 t9 MUST BE: RBUSTMG bit = 0 Parameter 4T if SLOW ARB = 0 opr if SLOW ARB = 1 from the trailing edge of nDS to ARB Page 50 DATASHEET t7 t14 Note 2 t8 t10 min max units ARB SMSC COM20019I 3.3V Rev.C ...
Page 51
... Data Register requires a minimum of 5T leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Figure 8.2 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE SMSC COM20019I 3.3V VALID DATA VALID t1 t2 ...
Page 52
... VALID DATA VALID t1 t2 t12 t5 t6 t13 t9 Parameter min Next )** * 4T ARB SLOW ARB = 0 opr from the trailing edge of nDS to the leading edge of the ARB from the trailing edge of nDS to ARB Page 52 DATASHEET t7 Note 2 t8** t8 t14 t10 max units SMSC COM20019I 3.3V Rev.C ...
Page 53
... Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Figure 8.4 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE SMSC COM20019I 3.3V VALID VALID DATA t1 t2, t4 ...
Page 54
... VALID DATA CASE 1: RBUSTMG bit = 0 min Parameter 4T to nRD Low if SLOW ARB = 0 opr if SLOW ARB = 1 opr from the trailing edge of nRD to the ARB from the trailing edge of nWR to the ARB Page 54 DATASHEET Note 2 t7 max units 5 ARB nS 40 SMSC COM20019I 3.3V Rev.C ...
Page 55
... Data Register requires a minimum of 5T leading edge of the next nRD. Note 3: Read cycle for Address Pointer Low/High Registers occurring after a write to Data Register requires a minimum of 5T leading edge of nRD. Figure 8.6 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE SMSC COM20019I 3.3V VALID t1 t3 Note 3 t5 ...
Page 56
... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM VALID t10 t8 CASE 1: RBUSTMG bit = 0 Parameter if SLOW ARB = 0 opr if SLOW ARB = 1 opr from the trailing edge of nDS to ARB Page 56 DATASHEET t11 Note 2 t9 VALID DATA min max units 5 ARB SMSC COM20019I 3.3V Rev.C ...
Page 57
... COM20019 cycles. Note 2: Read cycle for Address Pointer Low/High Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 8.8 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE SMSC COM20019I 3.3V VALID t10 ...
Page 58
... VALID DATA min Next )** 4T ARB 30*** SLOW ARB = 0 opr from the trailing edge of nWR to the leading edge ARB from the trailing edge of nWR to the ARB from the trailing edge of nRD to the ARB Page 58 DATASHEET Note 2 t5** t7 max units SMSC COM20019I 3.3V Rev.C ...
Page 59
... Register requires a minimum of 5T leading edge of the next nWR. Note 3: Write cycle for Address Pointer Low Register occurring after a read from Data Register requires a minimum of 5T leading edge of nWR. Figure 8.10 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE SMSC COM20019I 3.3V VALID t10 t6 ...
Page 60
... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM VALID t3 t5 t10 t8 VALID DATA min Next Time )** * 4T ARB 10 30*** from the trailing edge of nDS to the leading edge ARB from the trailing edge of nDS to ARB Page 60 DATASHEET t11 Note 2 t6 max units SMSC COM20019I 3.3V Rev.C ...
Page 61
... Any cycle occurring after a write to the Address Pointer Low Register requires a minimum the next nDS. Write cycle for Address Pointer Low Registers occurring after an access to Data Register requires a minimum of 5T the leading edge of the next nDS. Figure 8.11 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE SMSC COM20019I 3.3V VALID t10 t8 ...
Page 62
... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM t10 t12 t11 Parameter Page 62 DATASHEET t13 t8 LAST BIT (3200 nS BIT TIME) min typ max units - 1600* nS 3200 800* nS 800* nS 1600 -25 5500 5700 nS 3900 4100 nS 10 1600* nS 3200 SMSC COM20019I 3.3V Rev.C ...
Page 63
... High to Next nINTR Low Note period of external XTAL oscillation frequency. XTL Note**: T is period of Data Rate (i.e. at 312.5 Kbps Note***: When the power is turned on measured from stable XTAL oscillation after V DD Figure 8.15 - RESET AND INTERRUPT TIMING SMSC COM20019I 3.3V t2 1.0V min -200 t2 min ...
Page 64
... Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Package Outlines PIN 28L .160-.180 A .090-.120 .013-.021 .026-.032 B 1 .020-.045 C D .485-.495 .450-.456 .390-.430 D 3 .300 .050 BSC F .042-.056 G .042-.048 J .000-.020 R .025-.045 Page 64 DATASHEET SMSC COM20019I 3.3V Rev.C ...
Page 65
... E1 6.90 H 0. 0.50 Basic θ 0.17 R1 0.08 R2 0.08 ccc ~ ccc ~ Note 1: Controlling Unit: millimeter SMSC COM20019I 3.3V MAX ~ 1.6 0.10 0.15 1.40 1.45 9.00 9.20 1 4.50 4. Span Measure from Centerline 2 7.00 7.10 9.00 9.10 1 4.50 4. Span Measure from Centerline 2 7 ...
Page 66
... Setting the EF bit will change the minimum disable time to always be more than 200 nS. This is done by changing the clock which is supplied to the Interrupt Disable logic. The frequency of this clock is always less than 20MHz . B) Synchronize the Pre-Scalar Output Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 66 DATASHEET SMSC COM20019I 3.3V Rev.C ...
Page 67
... TA/RI bit, instead of at the start of the pulse. This is illustrated in Figure 10.1. EF=0 TA/RI bit Setting Pulse nINTR pin EF=1 TA/RI bit Setting Pulse nINTR pin Figure 10.1 - EFFECT OF THE EB BIT ON THE TA/RI BIT SMSC COM20019I 3.3V Tx/Rx completed prohibition period Tx/Rx completed Page 67 DATASHEET Rev. 11-07-08 ...
Page 68
... The soft reset is activated by the Node-ID register going to 00h or by the RESET bit going to High in the Configuration register. This solution is Enabled/Disabled by the EF bit. Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 68 DATASHEET SMSC COM20019I 3.3V Rev.C ...
Page 69
... SA15-SA4 P 12 SD7-SD0 A 8 nIOR nIOW SA2-SA0 3 IRQm nIOCS16 DRQn nDACK TC nREFRESH RESETDRV Figure 11.1 - EXAMPLE OF INTERFACE CIRCUIT DIAGRAM TO ISA BUS SMSC COM20019I 3.3V LS688x2 12 bit Comparators Q I/O Address Seeting (DIP Switches) P=Q 12 LS245 A 16 bit Bus Transceivers DIR 3 Schmitt-Trigger Buffer ...
Page 70
... If the value read from Register-5 is 0x80 then the part is a COM20019I 3V Rev the value read from Register-5 is 0xC0 then the part is a COM20019I 3V Rev C Rev. 11-07-08 Cost Competitive ARCNET (ANSI 878.1) Controller with On-Chip RAM Page 70 DATASHEET SMSC COM20019I 3.3V Rev.C ...