CS3310-KS Cirrus Logic Inc, CS3310-KS Datasheet
CS3310-KS
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CS3310-KS Summary of contents
Page 1
... The simple 3-wire interface provides daisy-chaining of multiple CS3310's for multi-channel audio systems. The device operates from ±5 V supplies and has an in- put/output voltage range of ±3.75 V. ORDERING INFORMATION CS3310-KS CS3310-KSZ, Lead Free + - MUX 8 8 Control Register ...
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... This parameter is guaranteed by design and/or characterization °C, VA+, VD ± 5%; VA- = -5V ± 5 Symbol Min - - - THD+N - 110 (VA-)+1.25 (Note 1) - (Note 2) -80 (Note 2) -100 (Note (Note 2) 2 IA+ - IA PSRR - CS3310 = L Typ Max Unit 0 ±0. ±0. kΩ 0.001 .0025 % 116 - dB - (VA+)-1.25 V µVrms 4.2 8 -110 - dB 0.25 0. 100 pF ...
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... Pulse Width High t ph Pulse Width Low t pl Pulse Width Low - t SDVS t SDH t CSVS t LTH t CSH t SSD t CSDH t CSVS t SDVS t SDH MSB t CSH t SSD Figure 1. Serial Port Timing Diagram CS3310 Min Typ Max 2.0 - VD+0.3 -0.3 - +0.8 VD-1 0 pF) L Min Typ Max ...
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... Positive Analog VA+ Negative Analog VA (VD+) - (VA+) (Note (AGND, DGND = 0V, all voltages with respect to ground.) Symbol Positive Digital VD+ Positive Analog VA+ Negative Analog VA IND STG CS3310 Min Typ Max 4.75 5.0 VA+ 4.75 5.0 5.25 -4.75 -5.0 -5.25 -0 Min Max -0.3 (VA+)+ 0.3 -0.3 6.0 ...
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... SDATAO when CS is high. **Refer to Note 3. Figure 2. Recommended Connection Diagram DS82F1 ** 0.1 µ F ZCEN VD+ VA SDATAI 6 CS3310 SCLK 8 SDATAO MUTE AINL AOUTL 9 AOUTR AINR DGND AGNDL AGNDR +5V ANALOG + 10 µ F 0.1 µ -5V ANALOG + 0.1 µ µ ANOTHER 7 CS3310 OR CONTROLLER * 47 k Ω 14 AUDIO 11 OUTPUTS CS3310 5 ...
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... The CS3310 operates from ±5 V supplies and accepts inputs up to ±3.75 V. Once in operation, the CS3310 can be brought to a muted state with the mute pin, MUTE writing all zeros to the volume control registers. The device contains a simple three wire serial interface which ac- cepts 16-bit data ...
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... SDATAO during the process. Multi-channel operation can be implemented as shown in Figure 4 by connecting the SDATAO of device #1 to the SDATAI pin of device #2. In this manner multiple CS3310s can be loaded from a single serial data line without complex addressing schemes. Volume control data is loaded by holding CS low for SCLK pulses, where N is the number of devices in the chain ...
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... Care has been taken to ensure that there are no audible artifacts in the analog output signal dur- ing volume control changes. The gain/attenuation changes of the CS3310 occur at zero cross- ings to eliminate glitches during level transitions. The zero crossing for the left channel is the voltage potential at the AGNDL pin ...
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... Power-Up Considerations Upon initial application of power, the MUTE pin of the CS3310 should be set low to initiate a pow- er-up sequence. This sequence sets the serial shift register and the volume control register to zero and performs an offset calibration. The device should remain muted until the supply voltag- es have settled to ensure an accurate calibration. The device also includes an internal power-on reset circuit that requires approximately 100 µ ...
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... Figure 6 is the Total Harmonic Distortion + Noise vs. amplitude at 1 kHz. The upper trace is the THD+N vs. amplitude of the CS3310 The lower trace is the THD+N of the Audio Precision Sys- tem One generator output connected directly to the analyzer input. The System One panel set- tings are identical to the previous test ...
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... Figure 16k FFT plot demonstrating the crosstalk performance of the CS3310 at 20 kHz. Both channels were set to unity gain. The right channel input is grounded with the left channel driven to 2.65 Vrms output at 20 kHz. The FFT plot is of the right channel output. This indicates channel to channel crosstalk of -130 kHz. Figure series of plots which display the unity-gain THD+N vs. Frequency for 600 Ω ...
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... Figure 9. Frequency Response -20 dB Input 0.1000 600 Ω 0.0100 2k Ω 0.0010 OPEN 0.0001 10k 20k 20 Figure 11. THD+N vs. Frequency Output levels of CS3310 AMPL (dBr) vs FREQ (Hz) Figure 7. 20 kHz Crosstalk AMPL (dBr) vs FREQ (Hz) 100 1k 10k 2.8 VRMS 2 VRMS 1 VRMS 100 1k 10k 1, 2, and 2 ...
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... VD+ DGND 5 12 SCLK 6 11 SDATAO 7 10 Mute MUTE 8 9 CS3310 AINL Left Channel Input AGNDL Left Analog Ground AOUTL Left Channel Output VA- Negative Analog Power VA+ Positive Analog Power AOUTR Right Channel Output AGNDR Right Analog Ground AINR Right Channel Input ...
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... CS3310 by the rising edge of SCLK. SDATAO - Serial Data Output, Pin 7. Serial output data that provides daisy-chaining of multiple CS3310’s. This serial output will output the previous sixteen bits of volume control data that were clocked into the SDATAI pin. SDATAO will enter a High Impedance State when CS is High. ...
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... kHz), including distortion components. Expressed in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter’s output with the input under test grounded and a full-scale signal applied to the other channel. Units in decibels. DS82F1 CS3310 15 ...
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... JEDEC #: MS-013 CS3310 c ∝ L MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.50 7.40 7.60 1.02 1.52 10.65 ...
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... OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. DS82F1 Changes CS3310 17 ...