CS5124 ON Semiconductor, CS5124 Datasheet
CS5124
Available stocks
Related parts for CS5124
CS5124 Summary of contents
Page 1
... Shutdown, Soft Start Timer, Low Voltage Current Sense for Resistive Sensing, Second Current Threshold for Pulse by Pulse Over Current Protection, a Direct Optocoupler Interface and Leading Edge Current Blanking. The CS5124/6 has supply range of 7 and is available in 8 pin SO narrow package. Features Line UVLO Monitoring ...
Page 2
... MAXIMUM RATINGS PIN NAME V Power Input CC Clock Synchronization Input V Clamp Output CC UVLO Shutdown Input Soft Start Capacitor Input Voltage Feedback Input Current Sense Input Ground Gate Drive Output CS5124, CS5126 CTX15–14514 510 k ZVN3310A D4 R4 BAS16LT1 10 Q2 IRFR220 C4 0. ...
Page 3
... Turn–on – Turn–off (– 100 C) Note 2 J Turn–on – Turn–off (100 C T 125 C) Note 2 J – With UVLO sinking 1.0 mA CS5124 Only. Connect an NFET as follows: BIAS = 200 nF C 500 nF 500 k Measure Voltage on BIAS with: ...
Page 4
... I SENSE Note 3 CS5126 Only At max duty cycle – 800 mV pulse into I (after blanking SENSE time 550 mV pulse into I SENSE Note 3 – CS5124 Only CS5126 Only – 6 1 OUT Series resistance < 1.0 Note 3 Series resistance < 1.0 Note Measure GATE rise time, 1.0 V < ...
Page 5
... CS5124, CS5126 PACKAGE PIN DESCRIPTION V V Power Input Pin BIAS V Clamp Output Pin. This pin will control the gate N–channel MOSFET that in turn regulates Vcc. This pin is internally clamped when the sleep mode. ...
Page 6
... THEORY OF OPERATION on the UVLO pin rises to between 1.8 V and 2.6 V the reference for the V regulated to 8 the BIAS pin (CS5124 only), but the IC remains in a UVLO state and the output driver does not switch. When the UVLO pin exceeds 2.6 V and the V exceeds 7.7 V, the GATE pin is released from a low state and at 8 ...
Page 7
... PWM comparator to provide high noise rejection with a low voltage across the current sense network. (The effective ramp is 21 mV/ s for the CS5124, and 18 mV/ s for the CS5126 (125 mV for the CS5126) nominal offset on the positive input to the PWM comparator allows for ...
Page 8
... UVLO pin shuts down the IC during high temperature operation, higher hysteresis (see hysteresis specification) might be required to enable the IC. BIAS Pin (CS5124 Only) The bias pin can be used to control V main application diagram in Figure 1. In order to provide adequate phase margin for the bias control loop, the pole created by the series pass transistor and the V capacitor should be kept above 10 kHz ...
Page 9
... 1st Threshold + 5.0 CS5124, CS5126 When the output current is high enough for the I to exceed the first threshold, the PWM cycle terminates early and the converter begins to function more like a current source. The current sense network must be chosen so that the = 8 ...
Page 10
... Two ways are shown in the application circuits. The CS5124 application circuit in Figure flyback converter that uses a second flyback winding to power V R4 improves V regulation with load changes by snubbing CC the turn off spike ...
Page 11
... –Y– –Z– PACKAGE THERMAL DATA Parameter CS5124, CS5126 PACKAGE DIMENSIONS SO–8 D SUFFIX CASE 751–07 ISSUE SO–8 Typical 45 Typical 165 http://onsemi.com 11 Unit C/W C/W ...
Page 12
... Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800–282–9855 Toll Free USA/Canada CS5124, CS5126 JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: r14525@onsemi ...