cy2212 Cypress Semiconductor Corporation., cy2212 Datasheet
cy2212
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cy2212 Summary of contents
Page 1
... CLK 4 13 VDDL CLKB 12 5 LCLK VSS 11 6 VSSL 10 VDD CLK,CLKB LCLK 300 MHz 9.375 MHz 400 MHz 9.375 MHz • 3901 North First Street • San Jose CY2212 CLK CLKB LCLK , CA 95134 • 408-943-2600 Revised January 12, 2005 [+] Feedback ...
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... Max. voltage on any pin with respect to ground I, ABS V Max. voltage on LCLK with respect to ground IL, ABS Crystal Requirements These are the requirements for the recommended crystal to be used with the CY2212 DRCG Lite clock source. The crystal load capacitance is internally set to 11 pF. Parameter X Frequency F [1] ...
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... LOH V LCLK Output low voltage at I LOL State Transition Characteristics Specifies the maximum settling time of the CLK, CLKB, and LCLK outputs from device power-up. For V any sequences are allowed to power-up and power-down the CY2212 DRCG-Lite. From CLK/CLKB/LCLK Normal DD DDL ...
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... These specifications refer to the logical and physical interfaces. Crystal Input The CY2212 receives its reference from an external crystal. Pin XIN is the reference crystal input, and pin XOUT is the reference crystal feedback. The parameters for the crystal are given on page 3 of this data sheet. ...
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... MID Measurement Point Figure 4. Output Driving Two Channels CY2212 is allowed. When the output is transi- OUT is to limit the maximum output P are used to control the output slew rate used to provide AC ground at MID resistors. P acceptable tolerance, assuming ...
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... This section defines the voltage and timing waveforms for the input and output pins of the CY2212. The Device Characteristics tables list the specifica- tions for the device parameters that are defined here. Input and Output voltage waveforms are defined as shown in Figure 5 ...
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... Figure 11 shows the definition of cycle-to-cycle duty cycle error. Cycle-to-cycle duty cycle error is defined as the difference between high-times of adjacent cycles. Equal requirements apply to the low-times vs. the 4CYCLE,i clock output cycle-to-cycle duty cycle error. CY2212 are possible This local cycle time CYCLE,LOCAL , which is the average CYCLE,AVG ...
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... Further details of jitter measurement methodologies are given JC,L in the Rambus DRCG-Lite Specification Appendix A published by Rambus, Inc. CY2212 t 4CYCLE,i+1 t PW+,i is defined J10 previously shown. Jitter J ...
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... REFERENCE JEDEC MO-153 6.25[0.246] PACKAGE WEIGHT 0.05 gms 6.50[0.256] Z16.173 ZZ16.173 LEAD FREE PKG. 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] SEATING PLANE CY2212 4 Cycle Jitter Operating Range Commercial Commercial Commercial Commercial MAX. PART # STANDARD PKG. 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] 51-85091-*A ...
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... Document History Page Document Title: CY2212 Direct Rambus™ Clock Generator (Lite) Document Number: 38-07466 Issue REV. ECN NO. Date ** 117801 12/10/02 *A 308300 See ECN Document #: 38-07466 Rev. *A Orig. of Change Description of Change CKN New Data Sheet RGL Corrected Ordering Info from - Added Lead Free Devices (-2) ...