CY23S09 Cypress Semiconductor, CY23S09 Datasheet

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CY23S09

Manufacturer Part Number
CY23S09
Description
(CY23S05 / CY23S09) Zero Delay Buffer
Manufacturer
Cypress Semiconductor
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07296 Rev. *B
Features
Functional Description
The CY23S09 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC
package. The CY23S05 is an eight-pin version of the
CY23S09. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at
Block Diagram
• 10-MHz to 100-/133-MHz operating range, compatible
• Zero input-output propagation delay
• Multiple low-skew outputs
• Less than 200 ps cycle-to-cycle jitter is compatible with
• Test Mode to bypass PLL (CY23S09 only, see Select
• Available in space-saving 16-pin, 150-mil SOIC, 4.4 mm
• 3.3V operation, advanced 0.65 CMOS technology
• Spread Aware™
REF
with CPU and PCI bus frequencies
Pentium -based systems
Input Decoding table on page 2)
TSSOP, and 150-mil SSOP ( CY23S09) or 8-pin, 150-mil
SOIC package (CY23S05)
— Output-output skew less than 250 ps
— Device-device skew less than 700 ps
— One input drives five outputs (CY23S05)
— One input drives nine outputs, grouped as 4 + 4 + 1
S2
S1
(CY23S09)
REF
PLL
PLL
CY23S09
CY23S05
Select Input
Decoding
Low-Cost 3.3V Spread Aware™ Zero Delay Buffer
MUX
3901 North First Street
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
CLK3
CLKOUT
CLK1
CLK2
CLK4
up to 100-/133-MHz frequencies, and have higher drive than
the -1 devices. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The CY23S09 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in the Select Input
Decoding table on page 2. If all output clocks are not required,
Bank B can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The CY23S09 and CY23S05 PLLs enter a power-down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0 A of current draw (for commercial temper-
ature devices) and 25.0
devices). The CY23S09 PLL shuts down in one additional
case, as shown in the table below.
Multiple CY23S09 and CY23S05 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle-to-cycle jitter. The
input to output propagation delay on both devices is
guaranteed to be less than 350 ps, and the output to output
skew is guaranteed to be less than 250 ps.
The CY23S05/CY23S09 is available in two different configu-
rations, as shown in the ordering information on page 6. The
CY23S05-1/CY23S09-1 is the base part. The CY23S05-1H/
CY23S09-1H is the high-drive version of the -1, and its rise
and fall times are much faster than -1.
San Jose
CLKA1
CLKA2
CLKB1
CLKB2
GND
REF
Pin Configuration
V
S2
CLK2
CLK1
DD
GND
REF
SOIC/TSSOP/SSOP
1
2
3
4
5
6
7
8
Top View
CY23S09
1
2
3
4
CA 95134
CY23S05
Top View
A (for industrial temperature
SOIC
Revised December 22, 2002
15
14
13
12
11
10
16
9
8
7
6
5
CLK4
V
CLK3
CLKOUT
CLKOUT
CLKA4
CLKA3
V
GND
CLKB4
CLKB3
S1
DD
DD
CY23S09
CY23S05
408-943-2600

Related parts for CY23S09

CY23S09 Summary of contents

Page 1

... REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY23S09 has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Select Input Decoding table on page 2. If all output clocks are not required, Bank B can be three-stated ...

Page 2

... For zero output-output skew, be sure to load all outputs equally. For further information, refer to the application note “CY23S05 and CY23S09 as PCI and SDRAM Buffers.” Note: 1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output. ...

Page 3

... Pin Description for CY23S09 Pin Signal [2] 1 REF [3] 2 CLKA1 [3] 3 CLKA2 GND [3] 6 CLKB1 [3] 7 CLKB2 [ [ [3] 10 CLKB3 [3] 11 CLKB4 12 GND [3] 14 CLKA3 [3] 15 CLKA4 [3] 16 CLKOUT Pin Description for CY23S05 Pin Signal ...

Page 4

... I Input HIGH Current IH V Output LOW Voltage OL V Output HIGH Voltage OH I (PD mode) Power-down Supply Current DD I Supply Current DD Switching Characteristics for CY23S05SC-1 and CY23S09SC-1 Commercial Temperature Devices Parameter Description t1 Output Frequency [7] Duty Cycle = t [7] t3 Rise Time [7] t Fall Time 4 t Output-to-Output Skew ...

Page 5

... Switching Characteristics for CY23S05SI-1H and CY23S09SI-1H Industrial Temperature Devices Parameter Description t1 Output Frequency [7] Duty Cycle = t [7] Duty Cycle = t [7] t3 Rise Time [7] t Fall Time 4 t Output-to-Output Skew 5 Delay, REF Rising Edge CLKOUT Rising Edge t Device-to-Device Skew 7 t Output Slew Rate ...

Page 6

... Test Circuits Test Circuit # 0.1 F OUTPUTS V DD 0.1 F GND Ordering Information Ordering Code CY23S05SC-1 CY23S05SC-1H CY23S09SC-1 CY23S09SC-1H CY23S09ZC-1 CY23S09ZC-1H CY23S09OC-1 CY23S09OC-1H Document #: 38-07296 Rev 2309– 0.1 F CLK out C LOAD 0.1 F GND For parameter t Package Name S8 8-pin 150-mil SOIC ...

Page 7

... Package Diagram Document #: 38-07296 Rev. *B 8-lead (150-Mil) SOIC S8 16-lead (150-Mil) Molded SOIC S16 CY23S05 CY23S09 51-85066-A 51-85068-A Page ...

Page 8

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 16-lead (150-mil) QSOP Q1 CY23S09 CY23S05 51-85091 ...

Page 9

... Document Title: CY23S09/CY23S05 Low-Cost 3.3V Spread Aware™ Zero Delay Buffer Document Number: 38-07296 Issue REV. ECN NO. Date ** 111147 11/14/01 *A 111773 02/20/02 *B 122885 12/22/02 Document #: 38-07296 Rev. *B Orig. of Change Description of Change DSG Change from spec number 38-01094 to 38-07296 CTK Add 150-mil SSOP option RBI ...

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