cy28445-5 SpectraLinear Inc, cy28445-5 Datasheet

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cy28445-5

Manufacturer Part Number
cy28445-5
Description
Clock Generator For Intel Calistoga Chipset
Manufacturer
SpectraLinear Inc
Datasheet
Rev 1.1, June 30, 2007
2200 Laurelwood Road, Santa Clara, CA 95054
Features
• Compliant to Intel
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 27 MHz Spread and Non-spread video clock
• 48 MHz USB clock
• SRC clocks independently stoppable through
• 96/100 MHz Spreadable differential video clock.
VTT_PW RG D#/PD
CLKREQ#
SEL_CLKREQ
FCTSEL[0:1]
CPU_STP#
PCI_STP#
CLKREQ #
ITP_SEL
FS[C:A]
SDATA
SCLK
XOUT
XIN
14.318M Hz
Crystal
Logic
I2C
27M Hz
LVDS
CPU
Fixed
PLL
PLL
PLL
PLL
Block Diagram
®
CK410M
PLL Reference
Divider
Divider
Divider
Divider
Clock Generator for Intel
VDD
REF
IREF
VDD
CPUT[0:1]
CPUC[0:1]
SRCT0/100M T_SST
SRCC0/100M C_SST
VDD
CPUT2_ITP/SRCT10
CPUC2_ITP/SRCC10
VDD48
PCIF[0:1]
VDD
VDD
SRCT[1:8]
SRCC[1:8]
VDD
PCI[1:5]
VDD_PCI
48M
27M - Spread
VDD48
27M - non Spread
DO T96T
VDD
VDD48
DO T96C
Tel:(408) 855-0555
DOT96T / 27MHz non spread
DOT96C/ 27MHz spread
SRCC_0 / LCD100MC 11
SRCT_0 / LCD100MT 10
VTT_PWRGD# / PD
x2 / x3
• 33 MHz PCI clock
• Buffered 14.318 MHz Reference Clock
• Low-voltage frequency select input
• I
• Ideal Lexmark Spread Spectrum profile for maximum
• 3.3V power supply
• 68-pin QFN (MLF) package
CLKREQ#_1
CPU
VDD_SRC 12
VDD_SRC 17
electromagnetic interference (EMI) reduction
48M/FSA
SRCC_1 14
SRCC_2 16
2
SRCT_1 13
SRCT_2 15
VDD48
VSS48
C support with readback capabilities
PCIF1
FSB
Fax:(408) 855-0550
x8/9/10
SRC
1
2
3
4
5
6
7
8
9
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
PCI
x7
Pin Configuration
REF
®
x2
CY28445-5
Calistoga Chipset
DOT96
x 1
www.SpectraLinear.com
USB_48M
CY28445-5
x 1
51 XIN
50 XOUT
49 VDD_REF
48 SDATA
47 SCLK
46 VSS_CPU
45 CPUT0
44 CPUC0
43 VDD_CPU
42 CPUT1
41 CPUC1
40 IREF
39 VSSA
38 VDDA
37 CPUT2_ITP / SRCT_10
36 CPUC2_ITP / SRCC_10
35 VDD_SRC
Page 1 of 26
LCD100M
x1
27M
x2

Related parts for cy28445-5

cy28445-5 Summary of contents

Page 1

... USB_48M x8/9/ Pin Configuration CY28445 www.SpectraLinear.com LCD100M 27M XIN 50 XOUT 49 VDD_REF 48 SDATA 47 SCLK 46 VSS_CPU 45 CPUT0 44 CPUC0 43 VDD_CPU ...

Page 2

... A precision resistor is attached to this pin, which is connected to the internal current reference. O, DIF Differential CPU clock outputs. PWR 3.3V power supply GND Ground I SMBus-compatible SCLOCK. I/O, OD SMBus-compatible SDATA. PWR 3.3V power supply O, SE 14.318 MHz crystal output. I 14.318 MHz crystal input. CY28445-5 Description Page ...

Page 3

... Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. CY28445-5 Description PIN 7 PIN 10 PIN 11 ...

Page 4

... Acknowledge from slave 37:30 Byte Count from slave – 8 bits 38 Acknowledge 46:39 Data byte 1 from slave – 8 bits 47 Acknowledge 55:48 Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge .... Stop CY28445-5 Page ...

Page 5

... Disabled Enabled 0 = Disable (Tri-state Enabled USB_48M MHz Output Enable 0 = Disabled Enabled REF0 Output Enable 0 = Disabled Enabled REF1 Output Enable 0 = Disabled Enabled CY28445-5 Byte Read Protocol Description Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Repeated start Slave address – ...

Page 6

... Allow control of SRC[T/C]2 with assertion of PCI_STP PCI_STP Free running Stopped with PCI_STP# Allow control of SRC[T/C]1 with assertion of PCI_STP PCI_STP Free running Stopped with PCI_STP# Allow control of SRC[T/C]0 with assertion of PCI_STP PCI_STP Free running Stopped with PCI_STP# CY28445-5 Description Description Description Page ...

Page 7

... Driven when PD asserted,1 = Tri-state when PD asserted Name REF/N or Tri-state Select 0 = Tri-state REF/N Clock Test Clock Mode Entry Control 0 = Normal operation REF/N or Tri-state mode, REF0 Output Drive Strength 0 = Low High REF0 Output Drive Strength 0 = Low High CY28445-5 Description Description Description Page ...

Page 8

... Name 0: –0.5% (Peak to peak) 1: –1.0% (Peak to peak) 0: Down Spread 1: Center Spread RESERVED, Set = 0 RESERVED, Set = 0 RESERVED, Set = 0 48-MHz Output Drive Strength 0 = Low High 33-MHz Output Drive Strength 0 = Low High 33-MHz Output Drive Strength 0 = Low High CY28445-5 Description Description Description Page ...

Page 9

... Allow control of SRC[T/C]10 with assertion of SW PCI_STP Free running Stopped with PCI_STP# RESERVED Allow control of SRC[T/C]8 with assertion of SW PCI_STP Free running Stopped with PCI_STP# Name RESERVED Set = 0 RESERVED RESERVED RESERVED 27M (Spread and Non-spread) Output Drive Strength 0 = Low High CY28445-5 Description Description Description Page ...

Page 10

... PCI4 (Spread and Non-spread) Output Drive Strength 0 = Low High PCI3 (Spread and Non-spread) Output Drive Strength 0 = Low High PCI2 (Spread and Non-spread) Output Drive Strength 0 = Low High Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED CY28445-5 Description Description Description Description Page ...

Page 11

... SRC[T/C]5 Control 0 = SRC[T/C]5 not stoppable by CLKREQ#5 1= SRC[T/C]5 stoppable by CLKREQ#5 SRC[T/C]4 Control 0 = SRC[T/C]4 not stoppable by CLKREQ SRC[T/C]4 stoppable by CLKREQ#5 SRC[T/C]3 Control 0 = SRC[T/C]3 not stoppable by CLKREQ SRC[T/C]3 stoppable by CLKREQ#5 SRC[T/C]2 Control 0 = SRC[T/C]2 not stoppable by CLKREQ SRC[T/C]2 stoppable by CLKREQ#5 CY28445-5 Description Description Description Page ...

Page 12

... SRC[T/C]6 Control 0 = SRC[T/C]6 not stoppable by CLKREQ SRC[T/C]6 stoppable by CLKREQ#3 SRC[T/C]5 Control 0 = SRC[T/C]5 not stoppable by CLKREQ SRC[T/C]5 stoppable by CLKREQ#3 SRC[T/C]4 Control 0 = SRC[T/C]4 not stoppable by CLKREQ SRC[T/C]4 stoppable by CLKREQ#3 SRC[T/C]3 Control 0 = SRC[T/C]3 not stoppable by CLKREQ SRC[T/C]3 stoppable by CLKREQ#3 CY28445-5 Description Description Description Page ...

Page 13

... AT Parallel The CY28445-5 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28445-5 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Rev 1.1, June 30, 2007 ...

Page 14

... C lock C hip Ci2 Cs1 XTAL Ce1 C e2 Figure 2. Crystal Loading Example Load Capacitance (each side – (Cs + Ci) Total Capacitance (as seen by the crystal CLe Ce1 + Cs1 + Ci1 Ce2 + Cs2 + Ci2 CY28445-5 Pin Cs2 Trace 2.8 pF Trim Page ...

Page 15

... Below is an example showing the relationship of clocks coming up. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. CY28445-5 Page ...

Page 16

... Synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles. Tdrive_CPU_STP >200 mV Figure 7. CPU_STP# Deassertion Waveform CY28445-5 Page ...

Page 17

... PCI_STP# PCI_F PCI SRC 100MHz Rev 1.1, June 30, 2007 Figure 10.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. ). (See SU Tsu Figure 10. PCI STP# Assertion Waveform CY28445-5 1.8 ms 1.8 ms Page ...

Page 18

... Sample Sels Delay VTT_PW RGD# State 1 State 2 On Figure 12. VTTPWRGD# Timing Diagram S1 VTT_PWRGD# = Low Delay >0.25mS S3 VDD_A = off Normal Operation VTT_PWRGD# = toggle CY28445-5 Device is not affected, VTT_PW RGD# is ignored State Sample Inputs straps Wait for <1.8ms Enable Outputs Page ...

Page 19

... SDATA, SCLK Typical Typical Except internal pull-up resistors, 0 < V Except internal pull-down resistors, 0 < – max. load and freq. per Figure 15 PD asserted, Outputs Driven PD asserted, Outputs Tri-state CY28445-5 Min. Max. Unit –0.5 4.6 –0.5 4.6 –0 0.5 VDC DD –65 150 ° ...

Page 20

... Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured from V = 0.175 0.525V OH Determined as a fraction of 2*(T – T )/( Math averages Figure 15 Math averages Figure 15 CY28445-5 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10 – 500 ps – 300 ppm 9.997001 10 ...

Page 21

... Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured at crossing point V Measured from 0.525V OH CY28445-5 Min. 250 – –0.3 – 9.997001 OX 9.997001 OX 9.872001 OX 9 ...

Page 22

... Measured at crossing point V Measured at crossing point V Measured from 0.525V OH Determined as a fraction of 2*(T – T )/( Math averages Figure 15 Math averages Figure 15 See Figure 15. Measure SE Measurement at 1.5V Measurement at 1.5V CY28445-5 Min. – – – 660 –150 250 – –0.3 – 45 29.99100 29.9910 29.49100 29 ...

Page 23

... Figure 14. Single-ended PCI, USB Load Configuration Condition Min. 20.48125 8.094 7.694 1.0 – – 27.000 27.000 10.5 10.5 1.0 – – 69.8203 68.82033 0.9 – – – – 10 CY28445-5 Max. Unit 21.18542 ns 11.036 ns 10.836 ns 2.2 V/ns 350 ps 100 ppm 55 % 27.0547 ns 27.0547 – ns – ns 4.0 V/ns 500 ps 0 ppm ...

Page 24

... Figure 15. 0.7V Differential Load Configuration Package Type CY28445 Product Flow Commercial Commercial ...

Page 25

... MAX 0.80[0.031] MAX 0°-12° C 68-Lead QFN (0.4-mm Pitch) LY68A ( Type II ) BOTTOM VIEW 0.18[0.007] 0.28[0.011] 0.08 C 0.05[0.002] MAX 6.30 REF 0.2[0.008] REF 0.45[0.017] 0.40[0.012] 0.50[0.020] 0.4 B.S.C. SEATING 0.25[0.009] MIN. PLANE 6.50[0.255] REF CY28445-5 PIN1 ID 0. 6.30 REF 0.24[0.009] 0.60[0.023] Page ...

Page 26

... Document History Page Document Title: CY28445-5 Clock Generator for Intel Orig. of REV. Issue Date Change 1.0 11/21/06 JMA 1.1 06/30/07 BSHEN While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in ...

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