CY29942 Cypress Semiconductor, CY29942 Datasheet

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CY29942

Manufacturer Part Number
CY29942
Description
1:18 Clock Distribution Buffer
Manufacturer
Cypress Semiconductor
Datasheet

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42
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Features
Cypress Semiconductor Corporation
Document #: 38-07284 Rev. *B
• 200-MHz clock support
• 2.5V or 3.3V operation
• LVCMOS/LVTTL clock input
• LVCMOS-/LVTTL-compatible inputs
• 18 clock outputs: drive up to 36 clock lines
• 200 ps max. output-to-output skew
• Output Enable control
• Pin compatible with MPC942C
• Available in Industrial and Commercial
• 32-pin LQFP package
Block Diagram
TCLK
OE
VDD
18
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
Q0-Q17
3901 North First Street
Description
The CY29942 is a low-voltage 200-MHz clock distribution buff-
er with an LVCMOS or LVTTL compatible input clock. All other
control inputs are LVCMOS/LVTTL compatible. The eighteen
outputs are 2.5V or 3.3V LVCMOS or LVTTL compatible and
can drive 50
For series terminated transmission lines, each output can
drive one or two traces giving the devices an effective fanout
of 1:36. Low output-to-output skews make the CY29942 an
ideal clock distribution buffer for nested clock trees in the most
demanding of synchronous systems.
Pin Configuration
TCLK
VDD
VDD
VSS
VSS
NC
OE
NC
San Jose
1
2
3
4
5
6
7
8
series or parallel terminated transmission lines.
CY29942
CA 95134
Revised December 21, 2002
24
23
22
21
20
19
18
17
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
CY29942
408-943-2600

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CY29942 Summary of contents

Page 1

... Cypress Semiconductor Corporation Document #: 38-07284 Rev. *B 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Description The CY29942 is a low-voltage 200-MHz clock distribution buff- er with an LVCMOS or LVTTL compatible input clock. All other control inputs are LVCMOS/LVTTL compatible. The eighteen outputs are 2.5V or 3.3V LVCMOS or LVTTL compatible and ...

Page 2

... PD = Internal Pull-Down Internal Pull-up. Document #: 38-07284 Rev. *B PWR I External Reference/Test Clock Input I, PU Output Enable. When HIGH, all the outputs are enabled. When set LOW, the outputs are at high impedance. VDD O Clock Outputs 3.3V or 2.5V Power Supply Common Ground No Connection CY29942 Description Page ...

Page 3

... Outputs @ 200 MHz 15pF 2.5V DD and V should be constrained to the in out < out Min. Typ. Max. VSS 0.8 2.0 VDD –200 200 0.5 2.4 2 285 335 200 240 CY29942 Unit V V µA µ Page ...

Page 4

... Across temperature and voltage ranges, includes output skew. 10. For a specific temperature and voltage, includes output skew. Pulse Generator ohm Figure 1. LVCMOS_CLK CY29942 Test Reference for V Figure 2. LVCMOS Propagation Delay (TPD) Test Reference Document #: 38-07284 Rev 3.3V ±5% or 2.5V ±5%, Over the specified temperature range DDC ...

Page 5

... Document #: 38-07284 Rev SK(0) Figure 4. Output-to-Output Skew tsk(0) CY29942 VCC VCC /2 GND VCC VCC /2 GND Page ...

Page 6

... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Type Commercial, 0°C to +70°C Commercial, 0°C to +70°C CY29942 Production Flow Industrial, -40°C to +85°C Industrial, -40°C to +85°C ...

Page 7

... Revision History Document Title: CY29942 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Document Number: 38-07284 Issue REV. ECN NO. Date ** 111095 02/07/02 *A 116777 08/14/02 *B 122876 12/21/02 Document #: 38-07284 Rev. *B Orig. of Change BRK New data sheet HWT Added a Commercial Temp. Range in the Ordering Information RBI Add power up requirements to maximum rating information. ...

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