CY62128B CYPRESS [Cypress Semiconductor], CY62128B Datasheet

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CY62128B

Manufacturer Part Number
CY62128B
Description
128K x 8 Static RAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-05300 Rev. *C
Features
Note:
Logic Block Diagram
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
• Temperature Ranges
• 4.5V – 5.5V operation
• CMOS for optimum speed/power
• Low active power
• Low standby power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
(70 ns, LL version, Commercial, Industrial)
— 82.5 mW (max.) (15 mA)
(70 ns, LL version, Commercial, Industrial)
— 110 µW (max.) (15 µA)
WE
CE 1
CE 2
OE
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
A 8
1
, CE
2
, and OE options
INPUT BUFFER
512x 256x 8
3901 North First Street
DECODER
COLUMN
ARRAY
POWER
DOWN
Functional Description
The CY62128B is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE
an active HIGH Chip Enable (CE
Enable (OE), and three-state drivers. This device has an
automatic
consumption by more than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable
One (CE
Enable Two (CE
through I/O
address pins (A
Reading from the device is accomplished by taking Chip
Enable One (CE
Write Enable (WE) and Chip Enable Two (CE
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH or CE
during a write operation (CE
The CY62128B is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
1
) and Write Enable (WE) inputs LOW and Chip
7
) is then written into the location specified on the
2
power-down
LOW), the outputs are disabled (OE HIGH), or
San Jose
0
2
1
) input HIGH. Data on the eight I/O pins (I/O
) and Output Enable (OE) LOW while forcing
through A
128K x 8 Static RAM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
,
CA 95134
16
1
feature
LOW, CE
).
[1]
0
through I/O
Revised February 14, 2005
2
), an active LOW Output
that
2
HIGH, and WE LOW).
7
reduces
CY62128B
) are placed in a
2
) HIGH. Under
408-943-2600
MoBL
power
1
),
0
1

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CY62128B Summary of contents

Page 1

... I/O pins. The eight input/output pins (I and OE options 1 2 high-impedance state when the device is deselected (CE HIGH or CE during a write operation (CE The CY62128B is available in a standard 450-mil-wide SOIC, 32-pin TSOP type I and STSOP packages. INPUT BUFFER 512x 256x 8 ARRAY POWER COLUMN DOWN DECODER • ...

Page 2

... ns. AA CY62128B MoBL Power Dissipation Operating, I Standby (mA) Speed [2] (ns) Typ. Max. Typ. 55 7 I/O ...

Page 3

... V – 0.3V ≤ 0.3V Test Conditions 32 SOIC 32 TSOP 32 STSOP 32 RTSOP 66.17 30.87 CY62128B MoBL Ambient [4] Temperature ( 0°C to +70°C –40°C to +85°C –40°C to +125°C CY62128B-55 CY62128B-70 [2] [2] Typ. Max. Min. Typ. 2.4 2.4 0.4 2 2.2 CC 0.3 0.8 –0.3 –1 +1 –1 –10 –1 +1 –1 – ...

Page 4

... Operating Range for “LL” version only) Conditions ≥ 2.0V ≤ 0.3V, V ≥ – 0.3V or DATA RETENTION MODE > min CDR CY62128B Max ALL INPUT PULSES V CC 90% 10% Rise TIme: 1 V/ns Min. Typ. 2.0 – 0.3V, 1.5 CC ≤ 0. min  ...

Page 5

... LOW to Power-down 2 HIGH to Write End OHA is less than less than t HZCE LZCE HZOE LZOE LOW, CE HIGH, and WE LOW CY62128B 62128B-55 62128B-70 Min. Max. Min. Max ...

Page 6

... Document #: 38-05300 Rev ACE t DOE t LZOE 50% [15, 16 SCE SCE PWE t SD DATA VALID transition LOW and CE transition HIGH CY62128B t HZOE t HZCE IMPEDANCE DATA VALID  MoBL HIGH Page ...

Page 7

... During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05300 Rev. *C [15, 16 SCE t SCE PWE t SD DATA IN [15, 16 SCE t SCE PWE t HZWE CY62128B VALID DATA VALID t LZWE  MoBL Page ...

Page 8

... CY62128BLL-55SI CY62128BLL-55SXI CY62128BLL-55SC CY62128BLL-55SXC CY62128BLL-55ZI CY62128BLL-55ZXI CY62128BLL-55ZAI CY62128BLL-55ZAXI CY62128BLL-55ZRI 70 CY62128BLL-70SI CY62128BLL-70SXI CY62128BLL-70SC CY62128BLL-70SXC CY62128BLL-70SE CY62128BLL-70SXE CY62128BLL-70ZI CY62128BLL-70ZXI CY62128BLL-70ZC CY62128BLL-70ZXC CY62128BLL-70ZE CY62128BLL-70ZXE CY62128BLL-70ZAI CY62128BLL-70ZAXI CY62128BLL-70ZAE CY62128BLL-70ZAXE CY62128BLL-70ZRXE Document #: 38-05300 Rev. *C I/O –I/O Mode 0 7 Power-down Power-down Read Write Selected, Outputs Disabled Package Name ...

Page 9

... MIL) Molded SOIC S34 1 0.546[13.868] 0.566[14.376] 0.440[11.176] 0.450[11.430] 32 0.006[0.152] 0.012[0.304] 0.118[2.997] MAX. 0.004[0.102] 0.004[0.102] MIN. SEATING PLANE CY62128B  MoBL 0.047[1.193] 0.063[1.600] 0.023[0.584] 0.039[0.990] 51-85081-*B 51-85056-*D Page ...

Page 10

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY62128B  ...

Page 11

... Document History Page  Document Title: CY62128B MoBL Document Number: 38-05300 Issue Orig. of REV. ECN NO. Date Change ** 116566 06/20/02 DSG *A 126601 06/09/03 *B 239134 See ECN AJU *C 321335 See ECN AJU Document #: 38-05300 Rev. *C 128K x 8 Static RAM Description of Change Changed from Spec number: 38-00524 to 38-05300 ...

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