DAC8420 Analog Devices, DAC8420 Datasheet
DAC8420
Specifications of DAC8420
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DAC8420 Summary of contents
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... VREFLO, is set by the user for positive or negative unipolar or bipolar signal swings within the supplies, allowing considerable design flexibility. The DAC8420 is available in 16-lead PDIP, SOIC, and CERDIP packages. Operation is specified with supplies ranging from +5 V only to ±15 V, with references of +2 ±10 V, respec- tively. Power dissipation when operating from ± ...
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... Using CLR and CLSEL .............................................................. 14 Programming the Analog Outputs .......................................... 14 VREFHI Input Requirements................................................... 16 Power-Up Sequence ................................................................... 16 Applications..................................................................................... 17 Power Supply Bypassing and Grounding................................ 17 Analog Outputs .......................................................................... 17 Reference Configuration ........................................................... 18 Isolated Digital Interface ........................................................... 19 Dual Window Comparator ....................................................... 20 MC68HC11 Microcontroller Interfacing................................ 20 DAC8420 to M68HC11 Interface Assembly Program .......... 21 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 23 Rev Page ...
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... V VREFHI −0.75 ±0.25 +0.75 = −5 V −1.0 −0.6 −1.25 +1.25 8 1.5 2.4 0 120 90 5 130 35 80 150 DAC8420 Unit LSB LSB LSB LSB LSB LSB LSB LSB LSB ppm/°C ppm/°C LSB − 2.5 V − 2.5 V − 2 μs V/μ μA ...
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... DAC8420 Parameter SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Power Dissipation 1 Typical values indicate performance measured at 25°C. 2 All supplies can be varied ±5% and operation is guaranteed. Device is tested with V 3 For single-supply operation ( V), due to internal offset errors INL and DNL are measured beginning at Code 0x005. ...
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... 2.4 0 0.002 0. −8 −5 255 DAC8420 1, 2 Unit LSB LSB LSB LSB LSB ppm/°C ppm/°C LSB − 2.5 V − 2 μs V/μ kHz μV μ ...
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... DAC8420 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter Rating V to GND −0.3 V, +18 GND +0.3 V, −18 −0.3 V, +36 −0 VREFLO +2 VREFHI VREFLO +2.0 V, +33.0 V VREFHI VREFHI VREFLO Digital Input Voltage to GND − ...
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... DUT 10µF 0.1µ 5kΩ 10kΩ 10µF 0.1µF 8 10kΩ CONNECT 10µF 0.1µF + Figure 3. Burn-In Diagram Rev Page DAC8420 t CSH LD2 t CLRW t S ±1LSB 5kΩ 10kΩ ...
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... Control Input, Determines action of CLR. If high, a clear command sets the internal DAC Register A through Register D to midscale (0x800). If low, the registers are set to zero (0x000). CLSEL is CMOS/ TTL compatible. Rev Page VDD CLSEL 1 16 VOUTD CLR 2 15 VOUTC DAC8420 VREFLO TOP VIEW (Not to Scale) VREFHI VOUTB CLK 6 11 VOUTA ...
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... Shifts register one bit 2 NC Shifts register one bit change change change Rev Page DAC8420 DAC Register A to DAC Register D Loads midscale value (0x800) Loads zero-scale value (0x000) Latches value No change No change 3 Loads the serial data-word 4 Transparent No change ...
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... DAC8420 TYPICAL PERFORMANCE CHARACTERISTICS 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –6 –4 – (V) VREFHI Figure 6. DNL vs. V (±15 V) VREFHI 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 –0.25 –0.30 1.5 2.0 2.5 V (V) VREFHI Figure 7. DNL vs. V VREFHI 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –6 –4 – (V) VREFHI Figure 8. INL vs. VREFHI (± ...
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... Rev Page DAC8420 T = +25° + +2.5V VREFHI VREFLO 500 1000 1500 2000 2500 3000 3500 4000 DIGITAL INPUT CODE Figure 15. Channel-to-Channel Matching T = +25° ...
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... DAC8420 1.5 1.0 0 –0 VREFHI V VREFLO –1.0 0 500 1000 1500 2000 2500 3000 DIGITAL INPUT CODE Figure 18. I vs. Code VREFHI –2.50µV LD 1.22mV 1 LSB 0mV –10.25mV –4.9µs 5µs/DIV t 8µs SETT Figure 19. Positive Settling Time (±5 V) 6.5mV ...
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... V = 2.02 µs 1M 10M 100k 1M 10 Rev Page DAC8420 +15V –15V +10V VREFHI V = –10V VREFLO ALL DACS HIGH (FULL SCALE TEMPERATURE (°C) Figure 27. Power Supply Current vs. Temperature ...
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... Output glitch impulse during major code transitions is a very low 64 nV-s (typ). DIGITAL INTERFACE OPERATION The serial input of the DAC8420, consisting SDI, and easily interfaced to a wide variety of microprocessor serial ports. While CS is low, the data presented to the input SDI is ...
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... VREFHI VREFLO ) + × VREFLO 2049 4096 − ( VREFHI VREFLO ) + × VREFLO 2048 4096 − ( VREFHI VREFLO ) + × VREFLO 2047 4096 − ( VREFHI VREFLO ) + × VREFLO 0 4096 Rev Page DAC8420 Note Full-scale output Midscale + 1 Midscale Midscale − 1 Zero scale ...
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... DAC8420 VREFHI INPUT REQUIREMENTS The DAC8420 utilizes a unique, patented DAC switch driver circuit that compensates for different supply, reference voltage, and digital code inputs. This ensures that all DAC ladder switches are always biased equally, ensuring excellent linearity under all conditions. Thus, as shown in Table 1, the VREFHI input of the DAC8420 requires both sourcing and sinking current capabili- ties from the reference voltage source ...
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... These amplifiers are short-circuit protected. The user should verify that the output load meets the capabilities of the device, in terms of both output current and load capacitance. The DAC8420 is stable with capacitive loads typically. 9 GND However, any capacitive load will increase the settling time, and should be minimized if speed is a concern ...
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... This is easily reduced by adding a simple RC low-pass filter on each output. REFERENCE CONFIGURATION The two reference inputs of the DAC8420 allow a great deal of flexibility in circuit design. The user must take care, however, to observe the minimum voltage input levels on VREFHI and VREFLO to maintain the accuracy shown in the data sheet ...
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... V less than the positive supply to ensure linearity of the device. For these applications, the REF43 is an excellent low drift 2.5 V reference that consumes only 450 μA (max). It works well with the DAC8420 in a single 5 V system as shown in Figure 34. +5V SUPPLY ...
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... DAC8420. Data is transmitted in 8-bit bytes (MSB first), with only eight rising clock edges occurring in the transmit cycle. To load data to the input register of the DAC8420, PC0 is taken low and held low during the entire loading cycle. The first eight bits are shifted in address first, immediately followed by another eight bits in the second least-significant byte to load the complete 16-bit word ...
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... DAC8420 TO M68HC11 INTERFACE ASSEMBLY PROGRAM * M68HC11 Register Definitions PORTC EQU $1003 Port C control register * “0,0,0,0;0,CLSEL,CLR,CS” DDRC EQU $1007 Port C data direction PORTD EQU $1008 Port D data register * “0,0,LD,SCLK;SDI,0,0,0” DDRD EQU $1009 Port D data direction SPCR EQU $1028 SPI control register * “ ...
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... DAC8420 OUTLINE DIMENSIONS 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.800 (20.32) 0.790 (20.07) 0.780 (19.81 0.280 (7.11) 0.250 (6.35) 1 0.240 (6.10) 8 0.100 (2.54) BSC 0.060 (1.52) MAX 0.015 (0.38) 0.015 (0.38) MIN GAUGE PLANE SEATING PLANE 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001-AB CONTROLLING DIMENSIONS ARE IN INCHES ...
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... DAC8420ESZ-REEL −40°C to +85°C DAC8420FP −40°C to +85°C 2 DAC8420FPZ −40°C to +85°C DAC8420FQ −40°C to +85°C DAC8420FS −40°C to +85°C DAC8420FS-REEL −40°C to +85°C 2 DAC8420FSZ −40°C to +85°C 2 DAC8420FSZ-REEL −40°C to +85°C 1 INL measured at VDD = +15 V and VSS = − ...
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... DAC8420 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00275-0-5/07(B) Rev Page ...