dm74as874 Fairchild Semiconductor, dm74as874 Datasheet

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dm74as874

Manufacturer Part Number
dm74as874
Description
Dual 4-bit D-type Edge-triggered Flip-flop
Manufacturer
Fairchild Semiconductor
Datasheet

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dm74as874NT
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© 2003 Fairchild Semiconductor Corporation
DM74AS874WM
DM74AS874NT
DM74AS874
Dual 4-Bit D-Type Edge-Triggered Flip-Flop
General Description
These dual 4-bit inverting registers feature totem-pole 3-
STATE outputs designed specifically for driving highly-
capacitive or relatively low-impedance loads. The high-
impedance state and increased high-logic-level drive pro-
vide these registers with the capability of being connected
directly to and driving the bus lines in a bus-organized sys-
tem without need for interface or pull-up components. They
are particularly attractive for implementing buffer registers,
I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the DM74AS874 are edge-triggered
D-type flip-flops. On the positive transition of the clock, the
Q outputs will be set to the logic states that were set up at
the D inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high-impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are OFF.
The pinout is arranged to ease printed circuit board layout.
All data inputs are on one side of the package, while all
outputs are on the other side.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
M24B
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
DS006331
Features
Switching specifications at 50 pF
Switching specifications guaranteed over full tempera-
ture and V
Advanced oxide-isolated, ion-implanted Schottky TTL
process
3-STATE buffer-type outputs drive bus lines directly
Space saving 300 mil wide package
Bus structured pinout
Package Description
CC
range
October 1986
Revised July 2003
www.fairchildsemi.com

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dm74as874 Summary of contents

Page 1

... They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the DM74AS874 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs ...

Page 2

Function Table Inputs CLR D CLK LOW State H HIGH State X Don’t Care Positive Edge Transition Z High Impedance ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Voltage Applied to Disabled Output Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V ...

Page 4

Switching Characteristics over recommended operating free air temperature range Symbol Parameter f Maximum Clock Frequency V MAX CC t Propagation Delay Time R PLH L LOW-to-HIGH Level Output Propagation Delay Time PHL HIGH-to-LOW Level Output t Output ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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