DP8390 NSC [National Semiconductor], DP8390 Datasheet

Page 1

... DP8390D NS32490D NIC Network Interface Controller General Description The DP8390D NS32490D Network Interface Controller (NIC microCMOS VLSI device designed to ease inter- facing with CSMA CD type local area networks including Ethernet Thin Ethernet (Cheapernet) and StarLAN The NIC implements all Media Access Control (MAC) layer func- ...

Page 2

Block Diagram 3 0 Functional Description (Refer to Figure 1 ) RECEIVE DESERIALIZER The Receive Deserializer is activated when the input signal Carrier Sense is asserted to allow incoming bits to be shift- ed into the shift register ...

Page 3

... NIC to ac- cept the packet Multicast addresses begin with an MSB of 2 bytes have ‘‘1’’ The DP8390D filters multicast addresses using a stan- dard hashing algorithm that maps all multicast addresses into a 6-bit value This 6-bit value indexes a 64-bit array that filters the value If the address consists of all 1’ ...

Page 4

... Connection Diagrams Plastic Chip Carrier Order Number DP8390DN or DP8390DV See NS Package Number N48A or V68A 5 0 Pin Descriptions BUS INTERFACE PINS Symbol DIP Pin No Function AD0 –AD15 1– 14–17 ADS0 8582 – 5 Description MULTIPLEXED ADDRESS DATA BUS Register Access with DMA inactive CS low and ACK returned from NIC pins AD0– ...

Page 5

Pin Descriptions (Continued) BUS INTERFACE PINS (Continued) Symbol DIP Pin No Function MWR MRD SWR 22 I SRD 23 I ACK 24 O RA0–RA3 45–48 I PRD 44 O ...

Page 6

... Direct Memory Access Control (DMA) The DMA capabilities of the NIC greatly simplify use of the DP8390D in typical configurations The local DMA channel transfers data between the FIFO and memory On transmis- sion the packet is DMA’d from memory to the FIFO in bursts Should a collision occur ( times) the packet ...

Page 7

Direct Memory Access Control (DMA) 32-Bit DMA Operation (Continued) Dual Bus System 7 0 Packet Reception The Local DMA receive channel uses a Buffer Ring Struc- ture comprised of a series of contiguous fixed length 256 byte (128 ...

Page 8

Packet Reception (Continued) for storing packets is controlled by Buffer Management Log the NIC The Buffer Management Logic provides three basic functions linking receive buffers for long packets re- covery of buffers when a packet is ...

Page 9

... For the DP8390D (but not e for the DP8390B) the NIC will be reset within 2 microseconds after the STP bit is set and Loopback mode 1 is programmed 3 Wait for at least Since the NIC will complete any transmission or reception that is in progress it is neces- ...

Page 10

Packet Reception (Continued) then the packet will essentially be lost and re-transmit- ted only after a time-out takes place in the upper level software By determining that the packet was lost at the driver level a transmit command ...

Page 11

Packet Reception (Continued) 3 After a packet is DMAed from the Receive Buffer Ring the Next Page Pointer (second byte in NIC buffer header) is used to update BNDRY and next pkt next pkt Next Page Pointer e ...

Page 12

Packet Transmission (Continued) TRANSMISSION Prior to transmission the TPSR (Transmit Page Start Regis- ter) and TBCR0 TBCR1 (Transmit Byte Count Registers) must be initialized To initiate transmission of the packet the TXP bit in the Command Register is ...

Page 13

Remote DMA (Continued) REMOTE WRITE A Remote Write transfer is used to move a block of data from the host into local buffer memory The Remote DMA will read data from the I O port and sequentially write ...

Page 14

Remote DMA (Continued) 2 Issue the ‘‘dummy’’ Remote Read command 3 Read the Current Remote DMA Address (CRDA) (both bytes) 4 Compare to previous CRDA value if different Delay and jump ...

Page 15

Remote DMA (Continued) Maximum Bus Latency for Byte Mode byte has entered the FIFO thus with an 8 byte threshold the NIC issues Bus Request (BREQ) when the 9th byte has entered the FIFO For Word Mode BREQ ...

Page 16

Remote DMA (Continued) Remote DMA Autoinitialization from Buffer Ring 10 0 Internal Registers All registers are 8-bit wide and mapped into two pages which are selected in the Command Register (PS0 PS1) Pins RA0–RA3 are used to address ...

Page 17

Internal Registers (Continued REGISTER ADDRESS ASSIGNMENTS Page 0 Address Assignments (PS1 e RA0 –RA3 RD 00H Command (CR) Command (CR) 01H Current Local DMA Page Start Register Address 0 (CLDA0) (PSTART) 02H Current Local DMA Page ...

Page 18

Internal Registers (Continued) Page 2 Address Assignments (PS1 RA0–RA3 RD 00H Command (CR) Command (CR) 01H Page Start Register Current Local DMA (PSTART) Address 0 (CLDA0) 02H Page Stop Register Current Local DMA (PSTOP) Address 1 (CLDA1) 03H ...

Page 19

Internal Registers (Continued Register Descriptions COMMAND REGISTER (CR) 00H (READ WRITE) The Command Register is used to initiate transmissions enable or disable Remote DMA operations and to select register pages To issue a command the microprocessor ...

Page 20

Internal Registers (Continued Register Descriptions (Continued) INTERRUPT STATUS REGISTER (ISR) This register is accessed by the host processor to determine the cause of an interrupt Any interrupt can be masked in the Interrupt Mask Register (IMR) ...

Page 21

Internal Registers (Continued Register Descriptions (Continued) INTERRUPT MASK REGISTER (IMR) 0FH (WRITE) The Interrupt Mask Register is used to mask interrupts Each interrupt mask bit corresponds to a bit in the Interrupt Status Register (ISR) If ...

Page 22

Internal Registers (Continued Register Descriptions (Continued) DATA CONFIGURATION REGISTER (DCR) This Register is used to program the NIC for 8- or 16-bit memory interface select byte ordering in 16-bit applications and establish FIFO threshholds The DCR ...

Page 23

Internal Registers (Continued Register Descriptions (Continued) TRANSMIT CONFIGURATION REGISTER (TCR) The transmit configuration establishes the actions of the transmitter section of the NIC during transmission of a packet on the network LB1 and LB0 which select ...

Page 24

Internal Registers (Continued Register Descriptions (Continued) TRANSMIT STATUS REGISTER (TSR) This register records events that occur on the media during transmission of a packet It is cleared when the next transmission is initiated by the host ...

Page 25

Internal Registers (Continued Register Descriptions (Continued) RECEIVE CONFIGURATION REGISTER (RCR) This register determines operation of the NIC during reception of a packet and is used to program what types of packets to accept 7 Bit Symbol ...

Page 26

Internal Registers (Continued Register Descriptions (Continued) RECEIVE STATUS REGISTER (RSR) 0CH (READ) This register records status of the received packet including information on errors and the type of address match either physical or multicast The contents ...

Page 27

Internal Registers (Continued DMA REGISTERS The DMA Registers are partitioned into three groups Trans- mit Receive and Remote DMA Registers The Transmit reg- isters are used to initialize the Local DMA Channel for trans- mission of ...

Page 28

Internal Registers (Continued) CURRENT PAGE REGISTER (CURR) This register is used internally by the Buffer Management Logic as a backup register for reception CURR contains the address of the first buffer to be used for a packet reception ...

Page 29

Internal Registers (Continued MAR0 FB7 FB6 FB5 FB4 FB3 FB2 MAR1 FB15 FB14 FB13 FB12 FB11 FB10 FB9 MAR2 FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16 MAR3 FB31 FB30 FB29 FB28 ...

Page 30

... Three forms of local loopback are provided on the NIC The user has the ability to loopback through the deserializer on the DP8390D NIC through the DP8391 SNI and to the coax to check the link through the transceiver circuitry Because of the half duplex architecture of the NIC loopback ...

Page 31

... UPPER BYTE COUNT LOOPBACK TESTS Loopback capabilities are provided to allow certain tests to be performed to validate operation of the DP8390D NIC pri transmitting and receiving packets on a live network Typically these tests may be performed during power node The diagnostic provides support to verify the follow- ...

Page 32

Loopback Diagnostics PATH TCR RCR TSR NIC External 04 00 43(1) Note 1 CDH is set CRS is not set since it is generated by the external encoder decoder PATH TCR RCR TSR NIC External 06 00 03(1) ...

Page 33

Bus Arbitration and Timing The NIC operates in three possible modes Upon power-up the NIC indeterminant state After receiving a Hardware Reset the NIC comes slave in the Reset State The receiver ...

Page 34

Bus Arbitration and Timing Note In 32-bit address mode ADS1 is at TRI-STATE after the first T1–T4 states thus pull-down resistor is required for 32-bit address mode (Continued) 16-Bit Address 16-Bit Data 32-Bit Address 8-Bit ...

Page 35

Bus Arbitration and Timing When in 32-bit mode four additional BSCK cycles are re- quired per burst The first bus cycle (T1 – each burst is used to output the upper 16-bit addresses This 16-bit ...

Page 36

Bus Arbitration and Timing REMOTE READ TIMING 1) The DMA reads byte word from local buffer memory and writes byte word into latch increments the DMA address and decrements the byte count (RBCR0 Request Line ...

Page 37

Bus Arbitration and Timing SLAVE MODE TIMING When CS is low the NIC becomes a bus slave The CPU can then read or write any internal registers All register access is byte wide The timing for register access ...

Page 38

Preliminary Electrical Characteristics Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Voltage ( ...

Page 39

... SRD or after SRD is de-asserted Note 3 These limits include the RC delay inherent in our test method These signals typically turn off within 15 ns enabling other devices to drive these lines with no contention AC Specs DP8390D Note All Timing is Preliminary Register Read (Latched Using ADS0) Min ...

Page 40

Switching Characteristics Register Read (Non Latched ADS0 Symbol Parameter rsrs Register Select to Read Setup (Notes 1 3) rsrh Register Select Hold from Read ackdv ACK Low to Valid Data rdz Read Strobe to Data TRI-STATE (Note 2) ...

Page 41

Switching Characteristics Symbol Parameter rss Register Select Setup to ADS0 Low rsh Register Select Hold from ADS0 Low aswi Address Strobe Width In rwds Register Write Data Setup rwdh Register Write Data Hold ww Write Strobe Width from ...

Page 42

Switching Characteristics Register Write (Non Latched ADS0 Symbol Parameter rsws Register Select to Write Setup (Note 1) rswh Register Select Hold from Write rwds Register Write Data Setup rwdh Register Write Data Hold wackl Write Low to ACK ...

Page 43

Switching Characteristics Symbol Parameter brqhl Bus Clock to Bus Request High for Local DMA brqhr Bus Clock to Bus Request High for Remote DMA brql Bus Request Low from Bus Clock backs Acknowledge Setup to Bus Clock (Note ...

Page 44

Switching Characteristics Symbol Parameter bcyc Bus Clock Cycle Time (Note 2) bch Bus Clock High Time bcl Bus Clock Low Time bcash Bus Clock to Address Strobe High bcasl Bus Clock to Address Strobe Low aswo Address Strobe ...

Page 45

Switching Characteristics Symbol Parameter bcrl Bus Clock to Read Strobe Low bcrh Bus Clock to Read Strobe High ds Data Setup to Read Strobe High dh Data Hold from Read Strobe High drw DMA Read Strobe Width Out ...

Page 46

Switching Characteristics Symbol Parameter bcwl Bus Clock to Write Strobe Low bcwh Bus Clock to Write Strobe High wds Data Setup to WR High wdh Data Hold from WR Low waz Write Strobe to Address TRI-STATE (Notes 1 ...

Page 47

Switching Characteristics Symbol Parameter ews External Wait Setup to T3 (Note 1) ewr External Wait Release Time (Note 1) Note 1 The addition of wait states affects the count of deserialized bytes and is limited to a number ...

Page 48

Switching Characteristics Symbol Parameter bpwrl Bus Clock to Port Write Low bpwrh Bus Clock to Port Write High prqh Port Write High to Port Request High (Note 1) prql Port Request Low from Read Acknowledge High rakw Remote ...

Page 49

Switching Characteristics Remote DMA (Read Send Command) Recovery Time Symbol Parameter bpwrl Bus Clock to Port Write Low bpwrh Bus Clock to Port Write High prqh Port Write High to Port Request High (Note 1) prql Port Request ...

Page 50

Switching Characteristics Symbol Parameter bprqh Bus Clock to Port Request High (Note 1) wprql WACK to Port Request Low wackw WACK Pulse Width bprdl Bus Clock to Port Read Low (Note 2) bprdh Bus Clock to Port Read ...

Page 51

Switching Characteristics Remote DMA (Write Cycle) Recovery Time Symbol Parameter bprqh Bus Clock to Port Request High (Note 1) wprql WACK to Port Request Low wackw WACK Pulse Width bprdl Bus Clock to Port Read Low (Note 2) ...

Page 52

Switching Characteristics Serial Timing Receive (Beginning of Frame) Symbol Parameter rch Receive Clock High Time rcl Receive Clock Low Time rcyc Receive Clock Cycle Time rds Receive Data Setup Time to Receive Clock High (Note 1) rdh Receive ...

Page 53

Switching Characteristics Serial Timing Transmit (Beginning of Frame) Symbol Parameter txch Transmit Clock High Time txcl Transmit Clock Low Time txcyc Transmit Clock Cycle Time txcenh Transmit Clock to Transmit Enable High (Note 1) txcsdv Transmit Clock to ...

Page 54

Switching Characteristics Symbol Parameter tcolw Collision Detect Width tcdj Delay from Collision to First Bit of Jam (Note 1) tjam Jam Period (Note 2) Note 1 The NIC must synchronize to collision detect If the NIC is in ...

Page 55

AC Timing Test Conditions Input Pulse Levels GND Input Rise and Fall Times Input and Output Reference Levels TRI-STATE Reference Levels Float ( V) Output Load (See Figure below) Note includes scope and ...

Page 56

... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Molded Dual-In-Line Package (N) Order Number DP8390DN NS Package Number N48A Plastic Chip Carrier (V) Order Number DP8390DV NS Package Number V68A 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life ...