dp8421a National Semiconductor Corporation, dp8421a Datasheet
dp8421a
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dp8421a Summary of contents
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... DP8422A is two access ports to simplify dual accessing Arbitration among these ports and refresh is done on chip of Pins of Address Control (PLCC) Outputs DP8420A 68 DP8421A 68 DP8422A 84 Block Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation Staggered Refresh trademark of National Semiconductor Corporation C 1995 National Semiconductor Corporation ...
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INTRODUCTION 2 0 SIGNAL DESCRIPTIONS 2 1 Address R W and Programming Signals 2 2 DRAM Control Signals 2 3 Refresh Signals 2 4 Port A Access Signals 2 5 Port B Access Signals (DP8422A Common ...
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Introduction The DP8420A 21A 22A are CMOS Dynamic RAM control- lers that incorporate many advanced features which include address latches refresh counter refresh clock row column and refresh address multiplexer delay line refresh access arbitration logic and high ...
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... Connection Diagrams Top View FIGURE 2 Order Number DP8420AV-20 or DP8420AV-25 See NS Package Number V68A Order Number DP8422AV-20 or DP8422AV- 8588 – 4 Order Number DP8421AV-20 or DP8421AV-25 See NS Package Number V68A Top View FIGURE 4 See NS Package Number V84A 8588 – 3 Top View FIGURE 3 ...
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... DRAM CONTROL SIGNALS Q0 – 10 DP8422A O Q0 – 9 DP8421A O Q0 – 8 DP8421A O RAS0 – CAS0 – (RFRQ) O Description ROW ADDRESS These inputs are used to specify the row address during an access to the DRAM They are also used to program the chip when ML is asserted (except ...
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Signal Descriptions (Continued) Pin Device (If not Input Name Applicable to All) Output 2 3 REFRESH SIGNALS RFIP O RFSH I DISRFSH PORT A ACCESS SIGNALS ADS I (ALE AREQ I WAIT ...
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Signal Descriptions (Continued) Pin Device (If not Input Name Applicable to All) Output 2 5 PORT B ACCESS SIGNALS AREQB DP8422A I only ATACKB DP8422A O only 2 6 COMMON DUAL PORT SIGNALS GRANTB DP8422A O only LOCK ...
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Programming and Resetting Due to the variety in power supplies power-up times the internal power up reset circuit may not work in every design therefore an EXTERNAL RESET must be performed before the DRAM controller can be programmed ...
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Programming and Resetting 3 2 PROGRAMMING METHODS Mode Load Only Programming To use this method the user asserts ML enabling the inter- nal programming register After ML is asserted a valid pro- gramming selection is ...
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Programming and Resetting 3 3 PROGRAMMING BIT DEFINITIONS Symbol ECAS0 Extend CAS Refresh Request Select 0 The CASn outputs will be negated with the RASn outputs when AREQ (or AREQB DP8422A only) is negated The WE output pin ...
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Programming and Resetting 3 3 PROGRAMMING BIT DEFINITIONS (Continued) Symbol RAS and CAS Configuration Modes (Continued RAS and CAS pairs are selected by B1 ECASn must be asserted for CASn to be ...
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Programming and Resetting 3 3 PROGRAMMING BIT DEFINITIONS (Continued) Symbol R5 R4 WAIT DTACK during Burst (See Section WAIT STATES during programming WAIT will ...
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Port A Access Modes The DP8420A 21A 22A have two general purpose access modes Mode 0 RAS synchronous and Mode 1 RAS asyn- chronous One of these modes is selected at programming through the B1 input A Port ...
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Port A Access Modes (Continued ACCESS MODE 1 Mode 1 asynchronous access is selected by asserting the e input B1 during programming (B1 1) This mode allows ac- cesses to start immediately from the access request ...
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Port A Access Modes (Continued EXTENDING CAS WITH EITHER ACCESS MODE In both access modes once AREQ is negated RAS and DTACK if programmed will be negated If ECAS0 was as- serted (0) during programming CAS ...
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Port A Access Modes (Continued READ-MODIFY-WRITE CYCLES WITH EITHER ACCESS MODE There are 2 methods by which this chip can be used to do read-modify-write access cycles The first method involves doing a late write access ...
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Port A Access Modes (Continued ADDITIONAL ACCESS SUPPORT FEATURES To support the different modes of accessing DP8420A 21A 22A offer other access features These ad- ditional features include Address Latches and Column In- crement (for page ...
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Port A Access Modes (Continued Address Pipelining Address pipelining is the overlapping of accesses to differ- ent banks of DRAM If the majority of successive accesses are to a different bank the accesses can be ...
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Port A Access Modes (Continued) 19 ...
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Port A Access Modes (Continued Delay CAS during Write Accesses Address bit C9 asserted during programming will cause CAS to be delayed until the first positive edge of CLK after RAS is asserted when the ...
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Refresh Options The DP8420A 21A 22A support three refresh control mode options 1 Automatic Internally Controlled Refresh 2 Externally Controlled Burst Refresh 3 Refresh Request Acknowledge With each of the control modes above three types of re- fresh ...
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Refresh Options (Continued Externally Controlled Burst Refresh To use externally controlled burst refresh the user must disable the automatic internally controlled refreshes by as- serting the input DISRFSH The user is responsible for gen- erating ...
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Refresh Options (Continued Refresh Request Acknowledge The DP8420A 21A 22A can be programmed to output in- ternal refresh requests When the user programs ECAS0 negated (1) and or address pipelining mode is selected the WE ...
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Refresh Options (Continued) 24 ...
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Refresh Options (Continued REFRESH CYCLE TYPES Three different types of refresh cycles are available for use The three different types are mutually exclusive and can be used with any of the three modes of refresh control ...
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Refresh Options (Continued Error Scrubbing during Refresh The DP8420A 21A 22A support error scrubbing during all RAS DRAM refreshes Error scrubbing during refresh is se- lected through bits C4 – C6 with bit R9 negated ...
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Refresh Options (Continued EXTENDING REFRESH The programmed number of periods of CLK that refresh RASs are asserted can be extended by one or multiple peri- ods of CLK Only the all RAS (with or without error ...
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Refresh Options (Continued CLEARING THE REFRESH REQUEST CLOCK The refresh request clock can be cleared by negating DISRFSH and asserting RFSH for 500 ns one period of the internal 2 MHz clock as shown in Figure ...
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Port A Wait State Support 6 2 DTACK TYPE OUTPUT With the R7 address bit asserted during programming the user selects the DTACK type output As long as DTACK is sampled negated by the CPU wait states are ...
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Port A Wait State Support FIGURE 24b WAITIN Example (WAIT is Sampled at the End of ‘‘T2’’ GUARANTEEING RAS LOW TIME AND RAS PRECHARGE TIME The DP8420A 21A 22A will guarantee RAS precharge time between accesses ...
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RAS and CAS Configuration Modes The DP8420A 21A 22A allow the user to configure the DRAM array to contain one two or four banks of DRAM Depending on the functions used certain considerations must be used when determining ...
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RAS and CAS Configuration Modes FIGURE 26c DRAM Array Setup for 16-Bit System ( FIGURE 26d 8 Bank DRAM Array for 16-Bit System ( (Continued during Programming ...
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RAS and CAS Configuration Modes 7 2 MEMORY INTERLEAVING Memory interleaving allows the cycle time of DRAMs to be reduced by having sequential accesses to different memory banks Since the DP8420A 21A 22A have separate pre- charge counters ...
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RAS and CAS Configuration Modes FIGURE 28a DRAM Array Setup for 4 Banks Using Address Pipelining ( (Also Allowing Error Scrubbing) during Programming) FIGURE 28b DRAM Array Setup ...
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RAS and CAS Configuration Modes 7 5 PAGE BURST MODE In a static column page or burst mode system the least significant bits must be tied to the column address in order to ensure that the page burst ...
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Test Mode Staggered refresh in combination with the error scrubbing mode places the DP8420A 21A 22A in test mode In this mode the 24-bit refresh counter is divided into a 13-bit and 11-bit counter During refreshes both counters ...
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Dual Accessing (DP8422A) The DP8422A has all the functions previously described In addition to those features the DP8422A also has the capa- bilities to arbitrate among refresh Port A and a second port Port B This allows two ...
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Dual Accessing (DP8422A PORT B WAIT STATE SUPPORT Advanced transfer acknowledge for Port B ATACKB is used for wait state support for Port B This output will be asserted when RAS for the Port B access ...
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Dual Accessing (DP8422A) Since the DP8422A has only one set of address inputs the signal is used with the addition of buffers to allow the cur- rently granted port’s addresses to reach the DP8422A The signals which need ...
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Dual Accessing (DP8422A) FIGURE 34b Wait States during a Port B Access LOCK Input When the LOCK input is asserted the currently granted port can ‘‘lock out’’ the other port through the insertion of wait ...
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Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Temperature under Bias b Storage Temperature Electrical Characteristics Symbol Parameter V Logical 1 ...
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AC Timing Parameters Two speed selections are given the DP8420A 21A 22A-20 and the DP8420A 21A 22A-25 The differences between the two parts are the maximum operating frequencies of the input CLKs and the maximum delay specifications Low ...
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AC Timing Parameters e Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except L e ...
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AC Timing Parameters e Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except L e ...
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AC Timing Parameters e Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except L e ...
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AC Timing Parameters e Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except L e ...
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AC Timing Parameters FIGURE 38 100 Port A and Port B Dual Access (Continued) FIGURE 37 100 Dual Access Port 8588 – 8588 – F1 ...
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AC Timing Parameters e Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except L e ...
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AC Timing Parameters e Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except L e ...
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AC Timing Parameters (Continued) FIGURE 40 300 Mode 0 Timing 8588 – F3 ...
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AC Timing Parameters (Programmed (Continued) FIGURE 41 300 Mode 0 Interleaving 8588 – F4 ...
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AC Timing Parameters e Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except L e ...
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AC Timing Parameters (Continued) FIGURE 42 400 Mode 1 Timing 8588 – F5 ...
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AC Timing Parameters FIGURE 43 400 COLINC Page Static Column Access Timing (Continued 8588 – F6 ...
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AC Timing Parameters e Unless otherwise stated 10 per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except L e ...
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AC Timing Parameters e Unless otherwise stated 10 DRAMs per bank including trace capacitance (Note 2) Two different loads are specified loads on all outputs except L ...
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Functional Differences between the DP8420A 21A 22A and the DP8420 Extending the Column Address Strobe (CAS) after AREQ Transitions High The DP8420A 21A 22A allows CAS to be asserted for an indefinite period of time ...
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... Physical Dimensions inches (millimeters) Order Number DP8420AV-20 DP8420AV-25 DP8421AV-20 or DP8421AV-25 Order Number DP8422AV-20 or DP8422AV-25 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein ...