DS21Q42 Dallas Semiconductor, DS21Q42 Datasheet

no-image

DS21Q42

Manufacturer Part Number
DS21Q42
Description
DS21Q42Enhanced QUAD T1 FRAMER
Manufacturer
Dallas Semiconductor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS21Q42
Manufacturer:
DS
Quantity:
48
Part Number:
DS21Q42
Manufacturer:
NXP
Quantity:
53 415
Part Number:
DS21Q42ES
Manufacturer:
DALLAS
Quantity:
48
Part Number:
DS21Q42N
Quantity:
168
Part Number:
DS21Q42T
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q42T
Manufacturer:
DALLAS
Quantity:
20 000
Part Number:
DS21Q42T
Manufacturer:
DALLAS
Quantity:
8 106
Part Number:
DS21Q42T+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q42TN
Manufacturer:
Maxim Integrated
Quantity:
10 000
FEATURES
DESCRIPTION
The DS21Q42 is an enhanced version of the DS21Q41B Quad T1 Framer. The DS21Q42 contains four
framers that are configured and read through a common microprocessor compatible parallel port. Each
framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. All
four framers in the DS21Q42 are totally independent, they do not share a common framing synchronizer.
Also the transmit and receive sides of each framer are totally independent. The dual two-frame elastic
stores contained in each of the four framers can be independently enabled and disabled as required. The
device fully meets all of the latest T1 specifications including ANSI T1.403–1995, ANSI T1.231–1993,
AT&T TR 62411 (12–90), AT&T TR54016, and ITU G.704 and G.706.
www.dalsemi.com
Four T1 DS1/ISDN–PRI/J1 framing
transceivers
All four framers are fully independent
Each of the four framers contain dual two–
frame elastic store slip buffers that can connect
to asynchronous backplanes up to 8.192 MHz
8–bit parallel control port that can be used
directly on either multiplexed or non–
multiplexed buses (Intel or Motorola)
Programmable output clocks for Fractional T1
Fully independent transmit and receive
functionality
Integral HDLC controller with 64-byte buffers
configurable for FDL or DS0 operation
Generates and detects in–band loop codes from
1 to 8 bits in length including CSU loop codes
Pin compatible with DS21Q44 E1 Enhanced
Quad E1 Framer
3.3V supply with 5V tolerant I/O; low power
CMOS
Available in 128–pin TQFP package
IEEE 1149.1 support
1 of 119
Enhanced QUAD T1 FRAMER
FUNCTIONAL DIAGRAM
ACTUAL SIZE
ORDERING INFORMATION
DS21Q42T
DS21Q42TN (-40
FRAMER #0
FRAMER #1
Form atter
Transm it
Receive
FRAMER #2
Fram er
FRAMER #3
(0
Control Port
0
C to 70
0
C to +85
FRAMER
QUAD
Elastic
Elastic
Store
Store
T1
0
C)
0
C)
DS21Q42
031500

Related parts for DS21Q42

DS21Q42 Summary of contents

Page 1

... IEEE 1149.1 support DESCRIPTION The DS21Q42 is an enhanced version of the DS21Q41B Quad T1 Framer. The DS21Q42 contains four framers that are configured and read through a common microprocessor compatible parallel port. Each framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. All four framers in the DS21Q42 are totally independent, they do not share a common framing synchronizer ...

Page 2

... INTRODUCTION The DS21Q42 is a superset version of the popular DS21Q41 Quad T1 framer offering the new features listed below. All of the original features of the DS21Q41 have been retained and software created for the original device is transferable to the DS21Q42. New Features Additional hardware signaling capability including: – ...

Page 3

... The clock applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock. The RSYSCLK can be a burst clock with speeds up to 8.192 MHz. The transmit side of the DS21Q42 is totally independent from the receive side in both the clock requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic store if necessary ...

Page 4

... DS21Q42 ENHANCED QUAD T1 FRAMER Figure 1 119 DS21Q42 ...

Page 5

... INTRODUCTION .............................................................................................................................. 2 2. DS21Q42 PIN DESCRIPTION ......................................................................................................... 8 3. DS21Q42 PIN FUNCTION DESCRIPTION ................................................................................ 15 4. DS21Q42 REGISTER MAP............................................................................................................. 22 5. PARALLEL PORT........................................................................................................................... 26 6. CONTROL, ID AND TEST REGISTERS ..................................................................................... 26 7. STATUS AND INFORMATION REGISTERS............................................................................. 37 8. ERROR COUNT REGISTERS....................................................................................................... 45 9. DS0 MONITORING FUNCTION................................................................................................... 48 10. SIGNALING OPERATION ............................................................................................................ 50 10.1. PROCESSOR BASED SIGNALING ................................................................................... 50 10.2. HARDWARE BASED SIGNALING ................................................................................... 52 11. PER– ...

Page 6

... TRANSMIT TRANSPARENCY .................................................................................................... 76 18. INTERLEAVED PCM BUS OPERATION ................................................................................... 76 19. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .......................... 79 19.1. DESCRIPTION ....................................................................................................................... 79 19.2. TAP CONTROLLER STATE MACHINE.............................................................................. 80 19.3. INSTRUCTION REGISTER AND INSTRUCTIONS ........................................................... 82 19.4. TEST REGISTERS ................................................................................................................. 84 20. TIMING DIAGRAMS ...................................................................................................................... 89 21. OPERATING PARAMETERS .................................................................................................... 104 22. 128-PIN TQFP PACKAGE SPECIFICATIONS ........................................................................ 119 6 of 119 DS21Q42 ...

Page 7

... DOCUMENT REVISION HISTORY Revision 12-22-98 Initial Release Notes 7 of 119 DS21Q42 ...

Page 8

... DS21Q42 PIN DESCRIPTION Pin Description Sorted by Pin Number Table 2-1 PIN SYMBOL 1 TCHBLK0 2 TPOS0 3 TNEG0 4 RLINK0 5 RLCLK0 6 RCLK0 7 RNEG0 8 RPOS0 9 RSIG0 [RCHCLK0] 10 RCHBLK0 11 RSYSCLK0 12 RSYNC0 13 RSER0 14 VSS 15 VDD 16 SPARE1 [RMSYNC0] 17 RFSYNC0 18 JTRST* [RLOS/LOTC0] 19 TCLK0 20 TLCLK0 21 TSYNC0 22 TLINK0 ...

Page 9

... Receive Clock for Framer 2 I Receive Bipolar Data for Framer 2 I Receive Bipolar Data for Framer 2 O Receive Signaling Output from Framer 2 [O] [Receive Channel Clock from Framer 2] - Signal Ground - Positive Supply Voltage O Receive Channel Block from Framer 119 DS21Q42 ...

Page 10

... Transmit Link Clock from Framer 3 I/O Transmit Sync for Framer 3 I Transmit Link Data for Framer 3 I/O Data Bus Bit or Address/Data Bit 0; LSB I/O Data Bus Bit or Address/Data Bit 1 I/O Data Bus Bit or Address/Data Bit 2 I/O Data Bus Bit or Address/Data Bit 3 I/O Data Bus Bit or Address/Data Bit 119 DS21Q42 ...

Page 11

... TSYSCLK0 126 TSER0 127 TSSYNC0 128 TSIG0 [TCHCLK0] Note: 1. Brackets [ ] indicate pin function when the DS21Q42 is configured for emulation of the DS21Q41B, (FMS = 1). TYPE DESCRIPTION I/O Data Bus Bit or Address/Data Bit 5 I/O Data Bus Bit or Address/Data Bit 6 I/O Data Bus Bit or Address/Data Bit 7; MSB I ...

Page 12

... Receive Clock for Framer 3 I Read Input (Data Strobe) O Receive Frame Sync from Framer 0 O Receive Frame Sync from Framer 1 O Receive Frame Sync from Framer 2 O Receive Frame Sync from Framer 3 O Receive Link Clock from Framer 119 DS21Q42 ...

Page 13

... Control for all Output and I/O Pins O Transmit Link Clock from Framer 0 O Transmit Link Clock from Framer 1 O Transmit Link Clock from Framer 2 O Transmit Link Clock from Framer 3 I Transmit Link Data for Framer 0 I Transmit Link Data for Framer 119 DS21Q42 ...

Page 14

... Transmit System Clock for Elastic Store in Framer 1 I Transmit System Clock for Elastic Store in Framer 2 I Transmit System Clock for Elastic Store in Framer 3 - Positive Supply Voltage - Positive Supply Voltage - Positive Supply Voltage - Signal Ground - Signal Ground - Signal Ground I Write Input (Read/Write 119 DS21Q42 ...

Page 15

... DS21Q42 PIN FUNCTION DESCRIPTION TRANSMIT SIDE PINS Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 1.544 MHz primary clock. Used to clock data through the transmit side formatter. Signal Name: TSER Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is disabled ...

Page 16

... A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Via TCR2.2, the DS21Q42 can be programmed to output either a frame or multiframe pulse at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to output double–wide pulses at signaling frames ...

Page 17

... CCR1.2, then this pin can be enabled input via RCR2.3 at which a frame or multiframe boundary pulse is applied. See Section 20 for details. Signal Name: RFSYNC Signal Description: Receive Frame Sync Signal Type: Output An extracted 8 KHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries 119 DS21Q42 ...

Page 18

... A 1.544 MHz reference clock used in the generation of 8MCLK. This function is available when FMS = 0. Signal Name: 8MCLK Signal Description: 8 MHz Clock Signal Type: Output A 8.192 MHz output clock that is referenced to the clock that is input at the CLKSI pin. This function is available when FMS = 119 DS21Q42 ...

Page 19

... HDLC Status Register. Active low, open drain output. Signal Name: FMS Signal Description: Framer Mode Select Signal Type: Input Set low to select DS21Q42 feature set. Set high to select DS21Q41 emulation. Signal Name: MUX Signal Description: Bus Operation Signal Type: Input Set low to select non– ...

Page 20

... Signal Type: Input Set high to 3–state all output and I/O pins (including the parallel control port) when FMS = 1 or when FMS = 0 and JTRST* is tied low. Set low for normal operation. Ignored when FMS = 0 and JTRST Useful in board level testing 119 DS21Q42 ...

Page 21

... Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left unconnected. This function is available when FMS = 0. SUPPLY PINS Signal Name: VDD Signal Description: Positive Supply Signal Type: Supply 2.97 to 3.63 volts. Signal Name: VSS Signal Description: Signal Ground Signal Type: Supply 0.0 volts 119 DS21Q42 ...

Page 22

... DS21Q42 REGISTER MAP Register Map Sorted by Address Table 4-1 ADDRESS R/W 00 R/W HDLC Control 01 R/W HDLC Status 02 R/W HDLC Interrupt Mask 03 R/W Receive HDLC Information 04 R/W Receive Bit Oriented Code 05 R Receive HDLC FIFO 06 R/W Transmit HDLC Information 07 R/W Transmit Bit Oriented Code 08 W Transmit HDLC FIFO 09 – Not used ...

Page 23

... R/W Transmit Channel 3 53 R/W Transmit Channel 4 54 R/W Transmit Channel 5 55 R/W Transmit Channel 6 56 R/W Transmit Channel 7 57 R/W Transmit Channel 8 REGISTER NAME 23 of 119 DS21Q42 REGISTER ABBREVIATION RMTCH2 RCR1 RCR2 RMR1 RMR2 RMR3 CCR3 RIR2 TCBR1 TCBR2 TCBR3 TCR1 TCR2 CCR1 CCR2 TTR1 TTR2 ...

Page 24

... R/W Receive Channel 1 81 R/W Receive Channel 2 82 R/W Receive Channel 3 83 R/W Receive Channel 4 84 R/W Receive Channel 5 85 R/W Receive Channel 6 REGISTER NAME 24 of 119 DS21Q42 REGISTER ABBREVIATION RC17 RC18 RC19 RC20 RC21 RC22 RC23 RC24 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 ...

Page 25

... Test Registers 1 and 2 are used only by the factory; these registers must be cleared (set to all zeros) on power– up initialization to insure proper operation. 2. Register banks AxH, BxH, CxH, DxH, ExH, and FxH are not accessible. REGISTER NAME 25 of 119 DS21Q42 REGISTER ABBREVIATION RC7 RC8 ...

Page 26

... MSB to determine which chip is present since in the DS21Q42 the MSB will be set to a zero and in the DS21Q44 it will be set to a one. The lower four bits of the IDR are used to display the die revision of the chip. ...

Page 27

... Sync Enable auto resync enabled 1 = auto resync disabled Resync. When toggled from low to high, a resynchronization of the receive side framer is initiated. Must be cleared and set again for a subsequent resync 119 DS21Q42 (LSB) ID2 ID1 ID0 (LSB) SYNCT SYNCE RESYNC ...

Page 28

... Fs–bit position; only Ft bit position 1 = report bit errors in Fs–bit position as well as Ft bit position Multiframe Out of Sync Count Register Function Select count errors in the framing bit position 1 = count the number of multiframes out of sync 28 of 119 DS21Q42 (LSB) RD4YM FSBE MOSCRF ...

Page 29

... TLINK pin Transmit Blue Alarm. (see note below transmit data normally 1 = transmit an unframed all one’s code at TPOS and TNEG Transmit Yellow Alarm. (see note below not transmit yellow alarm 1 = transmit yellow alarm 29 of 119 DS21Q42 (LSB) TFDLS TBL TYEL ...

Page 30

... I/O pins and parallel port pins) force all of the selected framer’s output pins high (excludes other framers I/O pins and parallel port pins 119 DS21Q42 (LSB) TSIO TD4YM TB7ZS ...

Page 31

... CCR1.0 Payload Loopback When CCR1.1 is set to a one, the DS21Q42 will be forced into Payload LoopBack (PLB). Normally, this loopback is only enabled when ESF framing is being performed but can be enabled also in D4 framing applications PLB situation, the DS21Q42 will loop the 192 bits of payload data (with BPVs corrected) from the receive section back to the transmit section ...

Page 32

... Framer Loopback When CCR1.0 is set to a one, the DS21Q42 will enter a Framer LoopBack (FLB) mode. This loopback is useful in testing and debugging applications. In FLB, the DS21Q42 will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur unframed all one’ ...

Page 33

... Error Counter Update Select. See Section 8 for details update error counters once a second 1 = update error counters every 42 ms (333 frames) Transmit Loop Code Enable. See Section 16 for details transmit data normally 1 = replace normal transmitted data with repeating code as defined in TCD register 33 of 119 DS21Q42 LSB) TLOOP TESMDM ...

Page 34

... Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits respectively. When the CCR3.3 is set to one, the DS21Q42 will force the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should be set to zero since B8ZS encoded data streams cannot violate the pulse density requirements ...

Page 35

... TDS0M register. See Section 9 for details. Transmit Channel Monitor Bit 3. Transmit Channel Monitor Bit 2. Transmit Channel Monitor Bit 1. Transmit Channel Monitor Bit 0. LSB of the channel decode 119 DS21Q42 (LSB) TCM2 TCM1 TCM0 ...

Page 36

... Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data will appear in the RDS0M register. See Section 9 for details. Receive Channel Monitor Bit 3. Receive Channel Monitor Bit 2. Receive Channel Monitor Bit 1. Receive Channel Monitor Bit 0. LSB of the channel decode 119 DS21Q42 (LSB) RCM1 RCM0 ...

Page 37

... HDLC and BOC controller. The specific details on the four registers pertaining to the HDLC and BOC controller are covered in Section 15 but they operate the same as the other status registers in the DS21Q42 and this operation is described below. ...

Page 38

... The user will always precede a read of any of the nine registers with a write. The byte written to the register will inform the DS21Q42 which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on ...

Page 39

... B8ZS Code Word Detect. Set when a B8ZS code word is detected at RPOS and RNEG independent of whether the B8ZS mode is selected or not via CCR2.6. Useful for automatically setting the line coding. Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing bit is received in error 119 DS21Q42 (LSB) SEFE B8ZS FBE ...

Page 40

... Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Receive AIS-CI Detect. Set when the AIS-CI pattern is detected 119 DS21Q42 (LSB) RBLC RPDV TPDV (LSB) - ...

Page 41

... RPOS and RNEG. Receive Yellow Alarm. Set when a yellow alarm is received at RPOS and RNEG. Receive Carrier Loss. Set when a red alarm is received at RPOS and RNEG. Receive Loss of Sync. Set when the device is not synchronized to the receive T1 stream 119 DS21Q42 (LSB) RCL RLOS ...

Page 42

... The blue alarm criteria in the DS21Q42 has been set to achieve this performance recommended that the RBL bit be qualified with the RLOS bit. ...

Page 43

... Receive FDL Match Occurrence. Set when the RFDL matches either RMTCH1 or RMTCH2. Receive FDL Abort. Set when eight consecutive one’s are received in the FDL. Receive Signaling Change. Set when the DS21Q42 detects a change of state in any of the robbed–bit signaling bits. SLIP RBL NAME AND DESCRIPTION Loop Up Code Detected ...

Page 44

... Transmit FDL Buffer Empty interrupt masked 1 = interrupt enabled Receive FDL Match Occurrence interrupt masked 1 = interrupt enabled Receive FDL Abort interrupt masked 1 = interrupt enabled Receive Signaling Change interrupt masked 1 = interrupt enabled 44 of 119 DS21Q42 (LSB) RMTCH RAF RSC ...

Page 45

... LCV3 LCV2 NAME AND DESCRIPTION MSB of the 16–bit code violation count LSB of the 16–bit code violation count B8ZS ENABLED? (CCR2. yes yes 45 of 119 DS21Q42 before this would occur). -2 (LSB) LCV9 LCV8 LCVCR1 LCV1 LCV0 LCVCR2 WHAT IS COUNTED IN THE LCVCRs ...

Page 46

... NAME AND DESCRIPTION MSB of the 12–Bit CRC6 Error or Frame Bit Error Count (note#2) LSB of the 12–Bit CRC6 Error or Frame Bit Error Count (note#2) COUNT Fs ERRORS? (RCR2.1) no yes don’t care 46 of 119 DS21Q42 (LSB) CRC/ CRC/ PCVCR1 FB9 FB8 CRC/ CRC/ PCVCR2 FB1 ...

Page 47

... MOS/ FB4 FB3 FB2 NAME AND DESCRIPTION MSB of the 12–Bit Multiframes Out of Sync or F–Bit Error Count (note #2) LSB of the 12–Bit Multiframes Out of Sync or F–Bit Error Count (note # 119 DS21Q42 (LSB) (note 1) (note 1) MOSCR 1 MOS/ MOS/ MOSCR FB1 FB0 ...

Page 48

... F–Bit 9. DS0 MONITORING FUNCTION Each framer in the DS21Q42 has the ability to monitor one DS0 64 Kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel monitored by properly setting the TCM0 to TCM4 bits in the CCR5 register ...

Page 49

... Must be cleared and set again for a subsequent align. See Section 13 for details. Receive Channel Monitor Bit 4. MSB of a channel decode that determines which receive channel data will appear in the RDS0M register. See Section 9 for details 119 DS21Q42 LSB (LSB) RCM2 ...

Page 50

... SIGNALING OPERATION Each framer in the DS21Q42 contains provisions for both processor based (i.e., software based) signaling bit access and for hardware based access. Both the processor based access and the hardware based access can be used simultaneously if necessary. The processor based signaling is covered in Section 10.1 and the hardware based signaling is covered in Section 10 ...

Page 51

... IMR2.0 bit. Once a signaling change has been detected, the user has at least 2. read the data out of the RS1 to RS12 registers before the data will be lost. A(5) A(4) A(3) A(13) A(12) A(11) A(21) A(20) A(19) B(5) B(4) B(3) B(13) B(12) B(11) B(21) B(20) B(19) A/C(5) A/C(4) A/C(3) A/C(13) A/C(12) A/C(11) A/C(21) A/C(20) A/C(19) B/D(5) B/D(4) B/D(3) B/D(13) B/D(12) B/D(11) B/D(21) B/D(20) B/D(19) NAME AND DESCRIPTION Signaling Bit D in Channel 24 Signaling Bit A in Channel 119 DS21Q42 (LSB) A(2) A(1) RS1 (60) A(10) A(9) RS2 (61) A(18) A(17) RS3 (62) B(2) B(1) RS4 (63) B(10) B(9) RS5 (64) B(18) B(17) RS6 (65) A/C(2) A/C(1) RS7 (66) A/C(10) A/C(9) RS8 (67) A/C(18) A/C(17) RS9 (68) B/D(2) B/D(1) RS10 (69) B/D(10) B/D(9) RS11 (6A) B/D(18) B/D(17) RS12 (6B) ...

Page 52

... The RSIG data is updated once a multiframe (1.5 ms) unless a freeze is in effect. See the timing diagrams in Section 20 for some examples. A(5) A(4) A(3) A(13) A(12) A(11) A(21) A(20) A(19) B(5) B(4) B(3) B(13) B(12) B(11) B(21) B(20) B(19) A/C(5) A/C(4) A/C(3) B/D(5) B/D(4) B/D(3) NAME AND DESCRIPTION Signaling Bit D in Channel 24 Signaling Bit A in Channel 119 LSB) A(2) A(1) TS1 (70) A(10) A(9) TS2 (71) A(18) A(17) TS3 (72) B(2) B(1) TS4 (73) B(10) B(9) TS5 (74) B(18) B(17) TS7 (75) A/C(2) A/C(1) TS7 (76) TS8 (77) B/D(2) B/D(1) TS10 (79) TS11 (7A) DS21Q42 ...

Page 53

... PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK Each framer in the DS21Q42 can replace data on a channel–by–channel basis in both the transmit and receive directions. The transmit direction is from the backplane to the T1 line and is covered in Section 11.1. The receive direction is from the T1 line to the backplane and is covered in Section 11.2. ...

Page 54

... Idle Code in the TIDR into this channel TIDR4 TIDR3 NAME AND DESCRIPTION MSB of the Idle Code (this bit is transmitted first) LSB of the Idle Code (this bit is transmitted last 119 (LSB) CH2 CH1 TIR1 (3C) CH10 CH9 TIR2 (3D) CH18 CH17 TIR3 (3E) TIDR2 TIDR1 DS21Q42 (LSB) TIDR0 ...

Page 55

... The first method which is covered in Section 11.2.1 was a feature contained in the original DS21Q41 while the second method which is covered in Section 11.2 new feature of the DS21Q42. 11.2.1 Simple Code Insertion The first method on the receive side involves using the Receive Mark Registers (RMR1/2/3) to determine which of the 24 T1 channels should be overwritten with either a 7Fh idle code or with a digital milliwatt pattern ...

Page 56

... RC register into the receive data stream 1 = insert data from the RC register into the receive data stream 56 of 119 (LSB) CH2 CH1 RMR1 (2D) CH10 CH9 RMR2 (2E) CH18 CH17 RMR3 (2F) (LSB RC1 (80) (LSB) CH2 CH1 RCC1 (1B) CH10 CH9 RCC2 (1C) CH18 CH17 RCC3 (1D) DS21Q42 ...

Page 57

... TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time 57 of 119 (LSB) CH2 CH1 RCBR1 (6C) CH10 CH9 RCBR2 (6D) CH18 CH17 RCBR3 (6E) (LSB) CH2 CH1 TCBR1 (32) CH10 CH9 TCBR2 (33) CH18 CH17 TCBR3 (34) DS21Q42 ...

Page 58

... ELASTIC STORES OPERATION Each framer in the DS21Q42 contains dual two–frame (386 bits) elastic stores, one for the receive direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert the T1 data stream to 2.048 Mbps (or a multiple of 2.048 Mbps) which is the E1 rate ...

Page 59

... HDLC CONTROLLER The DS21Q42 has an enhanced HDLC controller configurable for use with the Facilities Data Link or DS0s. There are 64 byte buffers in both the transmit and receive paths. The user can select any DS0 or multiple DS0s as well as any specific bits within the DS0(s) to pass through the HDLC controller. See Figure 20-15 for details on formatting the transmit side ...

Page 60

... The BOC controller will automatically detect incoming BOC sequences and alert the host. When the BOC ceases, the DS21Q42 will also alert the host. The user can set the device up to send any of the possible 6–bit BOC codes. ...

Page 61

... The real time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched. Like the other status registers in the DS21Q42, the user will always proceed a read of any of the four registers with a write. The byte written to the register will inform the DS21Q42 which of the latched bits the user wishes to read and have cleared (the real time bits are not affected by writing to the status register) ...

Page 62

... FIFO a1. if CBYTE=0 then skip to step 9 a2. if CBYTE=1 then skip to step REMPTY=1, then skip to step 10 9. Repeat step 8 10. Wait for interrupt, skip to step 8 11. If POK=0, then discard whole packet, if POK=1, accept the packet 12. disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 119 DS21Q42 ...

Page 63

... Transmit End of Message. Should be set to a one just before the last data byte of a HDLC packet is written into the transmit FIFO at THFR. The HDLC controller will clear this bit when the last byte has been transmitted 119 DS21Q42 (LSB) TZSD TCRCD ...

Page 64

... The setting of this bit prompts the user to read the THIR register for details. Transmit Message End. Set when the transmit HDLC controller has finished sending a message. The setting of this bit prompts the user to read the THIR register for details 119 DS21Q42 (LSB) THALF TNF TMEND ...

Page 65

... FIFO. Valid Message. Set when the HDLC controller has detected and checked a complete HDLC packet. Empty. A real–time bit that is set high when the receive FIFO is empty 119 DS21Q42 (LSB) THALF TNF TMEND (LSB) POK ...

Page 66

... BOC is currently being detected. BOC Bit 5. Last bit received of the 6–bit code word. BOC Bit 4. BOC Bit 3. BOC Bit 2. BOC Bit 1. BOC Bit 0. First bit received of the 6–bit code word 119 DS21Q42 (LSB) BOC1 BOC0 ...

Page 67

... Transmit FIFO Empty. A real–time bit that is set high when the FIFO is empty. Transmit FIFO Full. A real–time bit that is set high when the FIFO is full. Underrun. Set when the transmit FIFO unwantedly empties out and an abort is automatically sent 119 DS21Q42 (LSB) HDLC1 HDLC0 (LSB) TFULL UDR ...

Page 68

... HDLC Data Bit 7. MSB of a HDLC packet data byte. HDLC Data Bit 6. HDLC Data Bit 5. HDLC Data Bit 4. HDLC Data Bit 3. HDLC Data Bit 2. HDLC Data Bit 1. HDLC Data Bit 0. LSB of a HDLC packet data byte 119 DS21Q42 (LSB) BOC1 BOC0 (LSB) HDLC1 HDLC0 ...

Page 69

... DS0 Bit 3 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 2 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop this bit from being used 119 DS21Q42 (LSB) RD1 RD0 (LSB) RDB2 RDB1 ...

Page 70

... DS0 Bit 3 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 2 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop this bit from being used 119 DS21Q42 (LSB) TD1 TD0 (LSB) TDB2 TDB1 ...

Page 71

... If the zero destuffer sees six or more ones in a row followed by a zero, the zero is not removed. The CCR2.0 bit should always be set to a one when the DS21Q42 is extracting the FDL. More on how to use the DS21Q42 in FDL applications in this legacy support mode is covered in a separate Application Note. ...

Page 72

... If it finds such a pattern, it will automatically insert a zero after the five ones. The CCR2.0 bit should always be set to a one when the framer is inserting the FDL. More on how to use the DS21Q42 in FDL applications is covered in a separate Application Note. TFDL: TRANSMIT FDL REGISTER (Address = 7E Hex) [Also used to insert Fs framing pattern in D4 framing mode ...

Page 73

... PROGRAMMABLE IN–BAND CODE GENERATION AND DETECTION Each framer in the DS21Q42 has the ability to generate and detect a repeating bit pattern that is from one to eight bits in length. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition (TCD) register and select the proper length of the pattern by setting the TC0 and TC1 bits in the In– ...

Page 74

... Transmit Code Definition Bit 1. A Don’t Care bit length is selected. Transmit Code Definition Bit 0. A Don’t Care bit length is selected 119 LENGTH SELECTED 1 bits 2 bits 3 bits 4 bits 5 bits 6 bits 7 bits 8 bits C2 C1 DS21Q42 (LSB) C0 ...

Page 75

... Receive Down Code Definition Bit 2. A Don’t Care bit length is selected. Receive Down Code Definition Bit 1. A Don’t Care bit length is selected. Receive Down Code Definition Bit 0. A Don’t Care bit length is selected 119 DS21Q42 (LSB (LSB) C2 ...

Page 76

... The 8.192 MHz bus speed allows all four of the DS21Q42’s framers to share a common bus. Framers can interleave their data either on byte or frame boundaries. Framers that share a common bus must be configured through software and require several device pins to be connected together externally (see figures 18-1 & ...

Page 77

... In the 4.096 MHz bus configuration there is one master and one slave per bus. Figure 18-1 shows the DS21Q42 configured to support two 4.096 MHz buses. Bus 1 consists of framers 0 and 1. Bus 2 consists of framers 2 and 3. Framers 0 and 2 are programmed as master devices. Framers 1 and 3 are programmed as slave devices ...

Page 78

... TSER2 RSIG1 RSIG2 TSIG1 TSIG2 78 of 119 FRAMER 3 RSYSCLK3 TSYSCLK3 RSYNC3 TSSYNC3 RSER3 TSER3 RSIG3 TSIG3 SYSCLK SYNC INPUT RSER TSER RSIG TSIG Bus 2 FRAMER 3 RSYSCLK3 TSYSCLK3 RSYNC3 TSSYNC3 RSER3 TSER3 RSIG3 TSIG3 SYSCLK SYNC INPUT RSER TSER RSIG TSIG DS21Q42 ...

Page 79

... Boundary Scan Register Device Identification Register The JTAG feature is only available when the DS21Q42 feature set is selected (FMS = 0). The JTAG feature is disabled when the DS21Q42 is configured for emulation of the DS21Q41B (FMS = 1). Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994. The Test Access Port has the necessary interface pins ...

Page 80

... The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. Test-Logic-Reset Upon power up of the DS21Q42, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic of the DS21Q42 will operate normally. ...

Page 81

... Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is low during a rising edge on JTCLK. Exit2-IR A rising edge on JTCLK with JTMS low will put the controller in the Update-IR state. The controller will loop back to Shift-IR if JTMS is high during a rising edge of JTCLK in this state 119 DS21Q42 ...

Page 82

... IR state with JTMS high will move the controller to the Update-IR state The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS21Q42 with their respective operational binary codes are shown in Table 19-1. 1 ...

Page 83

... SAMPLE/PRELOAD A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the DS21Q42 can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the DS21Q42 to shift data into the boundary scan register via JTDI using the Shift-DR state. ...

Page 84

... DS21Q42 DS21Q44 HIGH Z All digital outputs of the DS21Q42 will be placed in a high impedance state. The BYPASS register will be connected between JTDI and JTDO. CLAMP All digital outputs of the DS21Q42 will output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction ...

Page 85

... SPARE1 - RFSYNCO O JTRST* I TCLK0 I TLCLK0 O TSYNC0.cntl - TSYNC0 I/O TLINK0 A6/ALE (AS) I INT* O TSYSCLK1 I TSER1 I TSSYNC1 I TSIG1 I TCHBLK1 O TPOS1 O TNEG1 O RLINK1 O RLCLK1 O RCLK1 119 DS21Q42 CONTROL BIT DESCRIPTION 0 = RSYNCO an input I = RSYNCO an output 0 = TSYNCO an input I = TSYNCO an output ...

Page 86

... FS1 I CS* I BTS I RD*/(DS*) I WR*/(R/W*) I MUX I TSYSCLK2 I TSER2 I TSSYNC2 I TSIG2 I TCHBLK2 O TPOS2 O TNEG2 O RLINK2 O RLCLK2 O RCLK2 I RNEG2 I RPOS2 I RSIG2 O VSS -79 VDD - RCHBLK2 O RSYSCLK2 I RSYNC2.cntl - 86 of 119 DS21Q42 CONTROL BIT DESCRIPTION 0 = RSYNC1 an input I = RSYNC1 an output 0 = TSYNC1 an input I = TSYNC1 an output 0 = RSYNC2 an input ...

Page 87

... VSS - VDD - CLKSI I TCLK3 I TLCLK3 O TSYNC3.cntl - TSYNC3 I/O TLINK3 I BUS.cntl - D0 or AD0 I AD1 I 119 DS21Q42 CONTROL BIT DESCRIPTION I = RSYNC2 an output 0 = TSYNC2 an input I = TSYNC2 an output 0 = RSYNC3 an input I = RSYNC3 an output 0 = TSYNC3 an input I = TSYNC3 an output 0 = D0-D7 or AD0-AD7 are inputs I = D0-D7 or AD0-AD7 are outputs ...

Page 88

... DEVICE SCAN PIN REGISTER BIT 119 91 120 90 121 89 122 88 123 87 124 86 125 85 126 84 127 83 128 82 SYMBOL TYPE D2 or AD2 I AD3 I AD4 I AD5 I AD6 I AD7 I/O TSYSCLK0 I TSER0 I TSSYNC0 I TSIG0 119 DS21Q42 CONTROL BIT DESCRIPTION ...

Page 89

... RSYNC in the frame mode (RCR2 and double-wide frame sync is enabled (RCR2 RSYNC in the multiframe mode (RCR2 RLINK data (Fs - bits) is updated one bit prior to even frames and held for two frames 5. RLINK and RLCLK are not synchronous with RSYNC when the receive side elastic store is enabled 89 of 119 DS21Q42 ...

Page 90

... RLINK data (FDL bits) is updated one bit time before odd frames and held for two frames 6. ZBTSI mode is enabled (RCR2 RLINK data (Z bits) is updated one bit time before odd frames and held for four frames 8. RLINK and RLCLK are not synchronous with RSYNC when the receive side elastic store is enabled 90 of 119 DS21Q42 ...

Page 91

... RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled) Figure 20-3 Notes: 1. There RCLK delay from RPOS/RNEG to RSER. 2. RCHBLK is programmed to block channel 24. 3. Shown is RLINK/RLCLK in the ESF framing mode 119 DS21Q42 ...

Page 92

... RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled) Figure 20-4 Notes: 1. RSYNC is in the output mode (RCR2 RSYNC is in the input mode (RCR2 RCHBLK is programmed to block channel 119 DS21Q42 ...

Page 93

... RSYNC is in the output mode (RCR2 RSYNC is in the input mode (RCR2 RCHBLK is forced to one in the same channels as RSER (see Note 1) 5. The F-Bit position is passed through the receive side elastic store and occupies the MSB position of channel 119 DS21Q42 ...

Page 94

... RECEIVE SIDE INTERLEAVED BUS OPERATION BYTE MODE TIMING Figure 20-6 Notes: 1. 4.096 MHz bus configuration. 2. 8.192 MHz bus configuration. 3. RSYNC is in the input mode (RCR2 119 DS21Q42 ...

Page 95

... RECEIVE SIDE INTERLEAVED BUS OPERATION FRAME MODE TIMING Figure 20-7 Notes: 1. 4.096 MHz bus configuration. 2. 8.192 MHz bus configuration. 3. RSYNC is in the input mode (RCR2 119 DS21Q42 ...

Page 96

... TSYNC in the frame mode (TCR2 and double-wide frame sync is enabled (TCR2 TSYNC in the multiframe mode (TCR2 TLINK data (Fs - bits) is sampled during the F-bit position of even frames for insertion into the outgoing T1 stream when enabled via TCR1.2 5. TLINK and TLCLK are not synchronous with TFSYNC 96 of 119 DS21Q42 ...

Page 97

... T1 stream if enabled via TCR1.2 6. ZBTSI mode is enabled (TCR2 TLINK data (Z bits) is sampled during the F-bit time of frames 13, 17, and 21 and inserted into the outgoing stream if enabled via TCR1.2 8. TLINK and TLCLK are not synchronous with TFSYNC 97 of 119 DS21Q42 ...

Page 98

... TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled) Figure 20-10 Notes: 1. There TCLK delay from TSER to TPOS/TNEG. 2. TSYNC is in the output mode (TCR2 TSYNC is in the input mode (TCR2 TCHBLK is programmed to block channel 2 5. Shown is TLINK/TLCLK in the ESF framing mode 98 of 119 DS21Q42 ...

Page 99

... TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled) Figure 20-11 Note: 1. TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored during channel 24 119 DS21Q42 ...

Page 100

... TCHBLK is forced to one in the same channels as TSER is ignored (see Note 1) 4. The F-bit position (MSB position of channel 1) for the T1 frame is sampled and passed through the transmit side elastic store (normally the transmit side formatter overwrites the F-bit position unless the formatter is programmed to pass-through the F-bit position) 100 of 119 DS21Q42 ...

Page 101

... TRANSMIT SIDE INTERLEAVED BUS OPERATION BYTE MODE TIMING Figure 20-13 Notes: 1. 4.096 MHz bus configuration. 2. 8.192 MHz bus configuration. 101 of 119 DS21Q42 ...

Page 102

... TRANSMIT SIDE INTERLEAVED BUS OPERATION FRAME MODE TIMING Figure 20-14 Notes: 1. 4.096 MHz bus configuration. 2. 8.192 MHz bus configuration. 102 of 119 DS21Q42 ...

Page 103

... DS21Q42 TRANSMIT DATA FLOW Figure 20-15 Notes: 1. TCLK should be tied to RCLK and TSYNC should be tied to RFSYNC for data to be properly sourced from RSER. 103 of 119 DS21Q42 ...

Page 104

... MIN TYP V 2 –0 2.97 DD MIN TYP OUT ( ° °C; VDD = 2.97 to 3.63V for DS21Q42T; -4 ° °C; VDD = 2.97 to 3.63V for DS21Q42TN) MIN TYP –1 –1 +4.0 OL 104 of 119 ( ° °C for DS21Q42T; ...

Page 105

... Pulse Width AS or ALE high Delay time ALE to DS, WR* or RD* Output Data Delay time from DS or RD* Data Set Up time (see Figures 21-1 to 21-3 for details) (0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21Q42T – 40ºC to +85ºC; VDD = 2.97 to 3.63V for DS21Q42TN) MIN TYP t 200 CYC PW 100 EL ...

Page 106

... WR* or DS* Inactive Data Hold Time from either WR* or DS* Inactive Address Hold from either WR* or DS* inactive See Figures 21–4 to 21–7 for details. (0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21Q42T; –40ºC to +85ºC; VDD = 2.97 to 3.63V for 21Q42TN) MIN TYP ...

Page 107

... Delay RSYSCLK to RSER, RSIG Valid Delay RSYSCLK to RCHCLK, RCHBLK, RMSYNC, RSYNC See Figures 21-8 to 21-10 for details. Notes: 1. RSYSCLK = 1.544 MHz. 2. RSYSCLK = 2.048 MHz. (0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21Q42T; –40ºC to +85ºC; VDD = 2.97 to 3.63V for DS21Q42TN) MIN TYP t 648 ...

Page 108

... TCHBLK, TCHBLK, TSYNC, TLCLK Delay TSYSCLK to TCHCLK, TCHBLK See Figures 21–11 to 21–13 for details. Notes: 1. TSYSCLK = 1.544 MHz. 2. TSYSCLK = 2.048 MHz. (0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21Q42T; –40ºC to +85ºC; VDD = 2.97 to 3.63V for DS21Q42TN) MIN TYP t 648 ...

Page 109

... INTEL BUS READ AC TIMING (BTS=0 / MUX = 1) Figure 21-1 INTEL BUS WRITE TIMING (BTS=0 / MUX=1) Figure 21-2 109 of 119 DS21Q42 ...

Page 110

... MOTOROLA BUS AC TIMING (BTS = 1 / MUX = 1) Figure 21-3 INTEL BUS READ AC TIMING (BTS=0 / MUX=0) Figure 21-4 110 of 119 DS21Q42 ...

Page 111

... INTEL BUS WRITE AC TIMING (BTS=0 / MUX=0) Figure 21-5 MOTOROLA BUS READ AC TIMING (BTS=1 / MUX=0) Figure 21-6 Note: 1. The signal DS is active high when emulating the DS21Q41 (FMS = 1). 111 of 119 DS21Q42 ...

Page 112

... MOTOROLA BUS WRITE AC TIMING (BTS=1 / MUX=0) Figure 21-7 Note: 1. The signal DS is active high when emulating the DS21Q41 (FMS = 1). 112 of 119 DS21Q42 ...

Page 113

... RECEIVE SIDE AC TIMING Figure 21-8 Notes: 1. RSYNC is in the output mode (RCR2.3 = 0). 2. Shown is RLINK/RLCLK in the ESF framing mode relationship between RCHCLK and RCHBLK and the other signals is implied. 113 of 119 DS21Q42 ...

Page 114

... RECEIVE SYSTEM SIDE AC TIMING Figure 21-9 Notes: 1. RSYNC is in the output mode (RCR2 RSYNC is in the input mode (RCR2 114 of 119 DS21Q42 ...

Page 115

... RECEIVE LINE INTERFACE AC TIMING Figure 21-10 115 of 119 DS21Q42 ...

Page 116

... TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled. 4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled. 5. TLINK is only sampled during F-bit locations relationship between TCHCLK and TCHBLK and the other signals is implied. 116 of 119 DS21Q42 ...

Page 117

... TRANSMIT SYSTEM SIDE AC TIMING Figure 21-12 Notes: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled. 117 of 119 DS21Q42 ...

Page 118

... TRANSMIT LINE INTERFACE SIDE AC TIMING Figure 21-13 118 of 119 DS21Q42 ...

Page 119

... TQFP Package Specifications 119 of 119 DS21Q42 ...

Related keywords