DS21Q50 Maxim Integrated Products, DS21Q50 Datasheet
DS21Q50
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DS21Q50 Summary of contents
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... GENERAL DESCRIPTION The DS21Q50 E1 quad transceiver contains all the necessary functions for connecting to four E1 lines. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. The DS21Q50 automatically adjusts to E1 22AWG (0.6mm) twisted-pair cables from 0km to over 2km in length ...
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INTRODUCTION ...............................................................................................................................6 2. PIN DESCRIPTION............................................................................................................................9 2 UNCTION ESCRIPTION 2.1.1 System (Backplane) Interface Pins .......................................................................................................15 2.1.2 Alternate Jitter Attenuator ....................................................................................................................16 2.1.3 Clock Synthesizer..................................................................................................................................16 2.1.4 Parallel Port Control Pins....................................................................................................................16 2.1.5 Serial Port Control Pins .......................................................................................................................17 2.1.6 Line ...
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CMI (CODE MARK INVERSION).................................................................................................64 18. INTERLEAVED PCM BUS OPERATION....................................................................................66 19. FUNCTIONAL TIMING DIAGRAMS...........................................................................................68 19 ECEIVE IMING IAGRAMS 19 RANSMIT IMING 20. OPERATING PARAMETERS ........................................................................................................74 21. AC TIMING PARAMETERS AND DIAGRAMS .........................................................................75 21.1 M ...
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... Figure 16-6. Jitter Attenuation.....................................................................................................................63 Figure 17-1. CMI Coding ............................................................................................................................64 Figure 17-2. CMI Code Violation Example ................................................................................................65 Figure 18-1. IBO Configuration Using Two DS21Q50 Transceivers (Eight E1 Lines) ............................67 Figure 19-1. Receive Frame and Multiframe Timing..................................................................................68 Figure 19-2. Receive Boundary Timing (With Elastic Store Disabled)......................................................68 Figure 19-3. Receive Boundary Timing (With Elastic Store Enabled) .......................................................69 Figure 19-4 ...
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Table 2-1. Pin Assignments (by Function) ....................................................................................................9 Table 2-2. Pin Assignment (by LQFP Pin Number)....................................................................................12 Table 3-1. Bus Mode Select.........................................................................................................................20 Table 3-2. Register Map ..............................................................................................................................23 Table 4-1. Sync/Resync Criteria..................................................................................................................26 Table 5-1. Alarm Criteria ............................................................................................................................34 Table 8-1. Transmit PRBS Mode Select......................................................................................................45 ...
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... The analog AMI/HDB3 waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of the DS21Q50. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive framer where the digital serial stream is analyzed to locate the framing/multiframe pattern ...
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Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125µs frame, there are 32 8-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and received first. These 32 time slots ...
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Figure 1-1. Block Diagram MCL VCO/PLL RECEIVE SIDE RRING1 RTIP1 TRANSMIT SIDE TRING1 TTIP1 TRANSCEIVER 1of 4 Parallel & Test Control Port (routed to all blocks) User Outputs Select Elastic Store DATA And CLOCK IBO Buffer SYNC Receive-Side Framer Sync ...
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PIN DESCRIPTION Table 2-1. Pin Assignments (by Function) PIN PARALLEL PORT ENABLED 71 4/8/16MCK AJACKI 69 AJACKO 50 ALE(AS)/A5 96 BTS0 97 BTS1 D0/AD0 20 ...
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NAME PIN PARALLEL PORT ENABLED 60 OUTB1 35 OUTB2 10 OUTB3 85 OUTB4 95 PBTS RD (DS REFCLK 67 RRING1 42 RRING2 17 RRING3 92 RRING4 63 RSER1 38 RSER2 13 RSER3 88 RSER4 64 RSYNC1 39 RSYNC2 ...
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PIN PARALLEL PORT ENABLED 56 TSER2 31 TSER3 6 TSER4 82 TSYNC1 57 TSYNC2 32 TSYNC3 7 TSYNC4 76 TTIP1 51 TTIP2 26 TTIP3 1 TTIP4 78 TVDD1 53 TVDD2 28 TVDD3 3 TVDD4 77 TVSS1 52 TVSS2 27 TVSS3 ...
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Table 2-2. Pin Assignment (by LQFP Pin Number) NAME PIN PARALLEL PORT ENABLED 1 TTIP4 2 TVSS4 3 TVDD4 4 TRING4 5 TCLK4 6 TSER4 7 TSYNC4 8 DVSS4 9 DVDD4 10 OUTB3 11 OUTA3 12 SYSCLK3 13 RSER3 14 ...
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NAME PIN PARALLEL PORT ENABLED ALE (AS)/A5 51 TTIP2 52 TVSS2 53 TVDD2 54 TRING2 55 TCLK2 56 TSER2 57 TSYNC2 58 DVSS2 59 DVDD2 60 OUTB1 61 OUTA1 ...
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NAME PIN PARALLEL PORT ENABLED 87 SYSCLK4 88 RSER4 89 RSYNC4 90 RVSS1 91 RTIP4 92 RRING4 93 RVDD1 94 INT 95 PBTS 96 BTS0 97 BTS1 TS0 100 TS1 — EQVSS1 — EQVSS2 — EQVSS3 — ...
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Pin Function Description 2.1.1 System (Backplane) Interface Pins Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 2.048MHz primary clock. Used to clock data through the transmit formatter. Signal Name: TSER Signal Description: Transmit Serial Data Signal ...
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Alternate Jitter Attenuator Signal Name: AJACKI Signal Description: Alternate Jitter Attenuator Clock Input Signal Type: Input Clock input to alternate jitter attenuator. Signal Name: AJACKO Signal Description: Alternate Jitter Attenuator Clock Output Signal Type: Output Clock output of alternate ...
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Signal Name: PBTS Signal Description: Parallel Bus Type Select Signal Type: Input Used to select between Motorola and Intel parallel bus types. Signal Name: AD0 to AD7/SDO Signal Description: Data Bus or Address/Data Bus [D0 to D6] Data Bus or ...
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Signal Name: ICES Signal Description: Input Clock Edge Select Signal Type: Input Used to select which SCLK clock edge samples data at SDI. Signal Name: OCES Signal Description: Output Clock Edge Select Signal Type: Input Used to select which SCLK ...
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Signal Name: DVSS Signal Description: Digital Signal Ground Signal Type: Supply 0V. Should be tied to the RVSS and TVSS pins. Signal Name: RVSS Signal Description: Receive Analog Signal Ground Signal Type: Supply 0V. Should be tied to DVSS and ...
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... Section 21 for more details. 3.2 Serial Port Operation Setting BTS1 pin = 1 and the BTS0 pin = 0 enables the serial bus interface on the DS21Q50. Port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section first. See ...
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Figure 3-1. Serial Port Operation Mode 1 ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK) OCES = 1 (UPDATE SDO ON RISING EDGE OF SCLK) SCLK SDI R/W (lsb) ...
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Figure 3-3. Serial Port Operation Mode 3 ICES = 0 (SAMPLE SDI ON THE RISING EDGE OF SCLK) OCES = 0 (UPDATE SDO ON FALLING EDGE OF SCLK) SCLK SDI R/W (lsb) ...
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Register Map Table 3-2. Register Map ADDRESS R R R/W 0B R/W 0C — 0D — 0E — 0F ...
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... The lower 4 bits of the device ID register are used to identify the revision of the device. This register exists in Transceiver 1 only (TS0, TS1 = 0). The test registers at addresses 1E, 1F, and 2F hex are used by the factory in testing the DS21Q50. On power-up, the test registers should be set to 00h in order for the DS21Q50 to operate properly. ...
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... Power-Up Sequence On power-up and after the supplies are stable, the DS21Q50 should be configured for operation by writing to all of the internal registers (this includes setting the test registers to 00h) since the contents of the internal registers cannot be predicted on power-up. The LIRST (CCR5.4) should be toggled from reset the line interface circuitry (it takes the device about 40ms to recover from the LIRST bit being toggled) ...
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... TSYNC is an input 1 = TSYNC is an output Note: See Figure 19-9 for more details about how the transmit control register affects the operation of the DS21Q50. RESYNC CRITERIA Three consecutive incorrect FAS received; Alternate (RCR1 the above criteria is met or three consecutive incorrect bit 2 of non-FAS received ...
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Register Name: CCR1 Register Description: Common Control Register 1 Register Address: 12 Hex Bit 7 6 Name FLB THDB3 NAME BIT Framer Loopback. See Section FLB loopback disabled 1 = loopback enabled Transmit HDB3 Enable THDB3 6 ...
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... Framer Loopback When CCR1.7 is set to 1, the DS21Q50 enters a framer loopback (FLB) mode loopback is useful in testing and debugging applications. In FLB, the SCT loops data from the transmitter back to the receiver. When FLB is enabled, the following occurs: 1) Data is transmitted as normal at TTIP and TRING. ...
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... FAS synchronization (if CRC4 is enabled). If any one (or more) of the above conditions is present, the framer transmits an RAI alarm. RAI generation conforms to ETS 300 011 specifications and a constant remote alarm is transmitted if the DS21Q50 cannot find CRC4 multiframe synchronization within 400ms as per G.706. ...
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... When CCR4.7 is set to 1, the DS21Q50 is forced into remote loopback (RLB). In this loopback, data input through the RTIP and RRING pins is transmitted back to the TTIP and TRING pins. Data continues to pass through the receive framer of the DS21Q50 as it would normally and the data from the transmit formatter is ignored (Figure 1-1) ...
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Register Name: CCR5 Register Description: Common Control Register 5 Register Address: 16 Hex Bit 7 6 Name LIUODO CDIG NAME BIT Line Interface Open-Drain Option. This control bit determines whether the TTIP and TRING outputs are open drain or not. ...
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... The write-read-write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS21Q50 with higher order software languages. The SSR register operates differently than the other three read-only register and reports the status of the synchronizer in real time ...
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Register Name: RIR Register Description: Receive Information Register Register Address: 08 Hex Bit 7 6 Name RGM1 RGM0 NAME BIT RGM1 7 Receive Gain Monitor Bit 1. See the Level Indication table below for level indication. RGM0 6 Receive Gain ...
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Register Name: SSR Register Description: Synchronizer Status Register Register Address: 09 Hex Bit 7 6 Name CSC5 CSC4 NAME BIT CSC5 7 CRC4 Sync Counter Bit 5. MSB of the 6-bit counter. CSC4 6 CRC4 Sync Counter Bit 4 CSC3 ...
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Register Name: SR1 Register Description: Status Register 1 Register Address: 0A Hex Bit 7 6 Name RSA1 RDMA NAME BIT Receive Signaling All Ones. Set when the contents of time slot 16 contain fewer than three RSA1 7 0s over ...
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Register Name: IMR1 Register Description: Interrupt Mask Register 1 Register Address: 18 Hex Bit 7 6 Name RSA1 RDMA NAME BIT Receive Signaling All Ones RSA1 interrupt masked 1 = interrupt enabled Receive Distant MF Alarm RDMA ...
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Register Name: SR2 Register Description: Status Register 2 Register Address: 0B Hex Bit 7 6 Name RMF RAF NAME BIT Receive CAS Multiframe. Set every 2ms (regardless if CAS signaling is enabled or not) RMF 7 on receive multiframe boundaries. ...
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Register Name: IMR2 Register Description: Interrupt Mask Register 2 Register Address: 19 Hex Bit 7 6 Name RMF RAF NAME BIT Receive CAS Multiframe RMF interrupt masked 1 = interrupt enabled Receive Align Frame RAF 6 0 ...
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... ERROR COUNT REGISTERS A set of four counters in each transceiver of the DS21Q50 record bipolar (BPV) or code violations (CV), errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. The E- bit counter is reconfigured for counting errors in the PRBS pattern if receive PRBS is enabled. Each of these four counters is automatically updated on either one-second boundaries (CCR2 ...
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CRC4 Error Counter CRC4 count register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 16-bit counter that records word errors in the cyclic redundancy check 4 (CRC4). Since the maximum CRC4 ...
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FAS Error Counter FAS count register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 16-bit counter that records word errors in the frame alignment signal (FAS) in time slot 0. This ...
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... DS0 MONITORING FUNCTION Each DS21Q50 framer can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel monitored by properly setting the TCM0 to TCM4 bits in the CCR3 register. In the receive direction, the RCM0– ...
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Register Name: TDS0M Register Description: Transmit Ds0 Monitor Register Register Address: 22 Hex Bit 7 6 Name B1 B2 NAME BIT Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit transmitted ...
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Register Name: RDS0M Register Description: Receive Ds0 Monitor Register Register Address: 2A Hex Bit 7 6 Name B1 B2 NAME BIT B1 7 Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit received Receive DS0 ...
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... PRBS GENERATION AND DETECTION The DS21Q50 can transmit and receive the 2 T O.151 specifications. The PRBS pattern can be unframed (in all 256 bits of the frame), framed (in all time slots except TS0 any single time slot. Register CCR5 contains the control bits for configuring the transmit and receive PRBS functions ...
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... DS21Q50s through the REFCLK pin. The REFCLK pin acts as an output on the DS21Q50, which has been selected to provide the reference clock from one of its four receivers. On DS21Q50s not selected to source the reference clock, this pin becomes an input by writing 0s to the SCSx bits ...
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... IBO circuit by dividing the clock present on the SYSCLK pin this configuration, if the signal present on the SYSCLK pin is lost, the DS21Q50 automatically switches to either the system reference clock or to the recovered clock off the same port, depending on which source the host assigned as the backup clock ...
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IDLE CODE INSERTION The transmit idle registers (TIR1/2/3/4) determine which of the 32 E1 channels should be overwritten with the code placed in the transmit idle-definition register (TIDR). This allows the same 8-bit code to be placed into any ...
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... ELASTIC STORE OPERATION The DS21Q50 contains a two-frame (512 bits) elastic store for the receive direction. The elastic store is used to absorb the differences in frequency and phase between the E1 data stream and an asynchronous (i.e., not frequency locked) backplane clock that can be 2.048MHz for normal operation or 4.096MHz, 8 ...
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ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION On the receiver, the RAF and RNAF registers always report the data received in the additional (Sa) and international (Si) bit locations. The RAF and RNAF registers are updated ...
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... Additional Bit 7 Sa8 0 Additional Bit 8 Register Name: TAF Register Description: Transmit Align Frame Register Register Address: 20 Hex (Must be programmed with the 7-bit FAS word; the DS21Q50 does not automatically set these bits.) Bit 7 6 Name Si 0 NAME BIT Si 7 International Bit ...
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... Register Name: TNAF Register Description: Transmit Nonalign Frame Register Register Address: 21 Hex (Bit 6 must be programmed to 1; the DS21Q50 does not automatically set this bit.) Bit 7 6 Name Si 1 NAME BIT Si 7 International Bit 1 6 Frame Nonalignment Signal Bit. Set this bit = 1. ...
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USER-CONFIGURABLE OUTPUTS There are two user-configurable output pins for each transceiver, OUTA and OUTB. These pins can be programmed to output various clocks, alarms for line monitoring, logic 0 and 1 levels to control external circuitry, or access transmit ...
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Register Name: OUTBC Register Description: OUTB Control Register Register Address: 1B Hex Bit 7 6 Name NRZE — NAME BIT NRZ Enable. When this bit is set, the receiver can accept TTL-type NRZ data at the RTIP input. RRING becomes ...
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Table 15-1. OUTA and OUTB Function Select OA3 OA2 OA1 OA0 OB3 OB2 OB1 OB0 ...
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... LINE INTERFACE UNIT The line interface unit in the DS21Q50 contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the E1 line; and the jitter attenuator. The line interface control register (LICR), described below, controls each of these three sections. ...
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... E1 line termination resistors (Rt) and the monitor port isolation resistors (Rm) as shown in Figure 16-1. The four receivers of the DS21Q50 can provide gain to overcome the resistive loss of a monitor connection. This is typically a purely resistive loss/gain and should not be confused with the cable loss characteristics transmission line. By setting the receive monitor mode register as ...
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Register Name: RMM Register Description: Receive Monitor Mode Register Register Address: 1F Hex Bit 7 6 Name 0 MM1 NAME BIT — 7 Reserved. Must be set = 0 for proper operation 6 Monitor Mode 2. Sets the internal linear ...
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... E1 line. The waveforms meet the ITU G.703 specifications (Figure 16-4). The user selects which waveform generated by properly programming the L2/L1/L0 bits in the LICR. The DS21Q50 can be set number of various configurations, depending on the application Table 16-3. Line Build-Out Select in LICR L2 ...
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... C1 polarized +VDD 0.1mF +3.3V 0.1mF DVDD DVSS 0.01mF RVDD 0.1mF RVSS TVDD 0.1mF TVSS MCLK 2.048MHz 0.1mF TTIP1 DVDD DVSS 0.01mF TRING1 RVDD 0.1mF RVSS TVDD 0.1mF TVSS 1/4 DS21Q50 RTIP1 2.048MHz MCLK RRING1 +VDD 68mF ...
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Figure 16-4. Transmit Waveform Template 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 194ns 219ns -200 -150 -100 -50 0 TIME (ns 269ns G.703 Template 50 100 150 200 ...
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... TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120 UI depth is 32 bits), the DS21Q50 divides the internal nominal 32.768MHz clock by either instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17, it also sets the JALT bit in the receive information register (RIR ...
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... Figure 16-5. Jitter Tolerance 1K 100 0.1 1 Figure 16-6. Jitter Attenuation 0dB -20dB -40dB -60dB 1 Ds21Q50 Tolerance 1.5 Minimum Tolerance Level as per ITU G.823 20 10 100 1K FREQUENCY (Hz) Prohibited Area ETS 300 011 & TBR12 Prohibited Area 40 10 100 1K FREQUENCY (Hz 0.2 2.4K 18K 10K 100K ITU G ...
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... CMI (CODE MARK INVERSION) The DS21Q50 provides a CMI interface for connection to optical transports. This interface is a unipolar 1T2B-coded signal. Ones are alternately encoded as a logical level for the full duration of the clock period. Zeros are encoded as a 0-to-1 transition at the middle of the clock period. ...
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Transmit and receive CMI is enabled through OUTAC.7. When this register bit is set, the TTIP pin outputs CMI-coded data at normal TTL-type levels. This signal can be used to directly drive an optical interface. When CMI is enabled, the ...
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... In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS21Q50 can be configured to allow PCM data buses to be multiplexed into higher speed data buses, eliminating external hardware, saving board space and cost ...
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... SCS0 Figure 18-1. IBO Configuration Using Two DS21Q50 Transceivers (Eight E1 Lines) Note: See Section 16 for details about the line interface circuit. FUNCTION 2.048MHz, Single device on bus 4.096MHz, Two devices on bus 8.192MHz, Four devices on bus 16.384MHz, Eight devices on bus ...
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FUNCTIONAL TIMING DIAGRAMS 19.1 Receive Timing Diagrams Figure 19-1. Receive Frame and Multiframe Timing 1 FRAME RSYNC 2 RSYNC NOTE 1: RSYNC IN FRAME/OUTPUT MODE (RCR.6 = 0). NOTE 2: RSYNC IN MULTIFRAME/OUTPUT MODE (RCR.6 = 1). ...
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Figure 19-3. Receive Boundary Timing (With Elastic Store Enabled) SYSCLK CHANNEL 31 RSER 1 RSYNC 2 RSYNC NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR.5 = 0). NOTE 2: RSYNC IS IN THE INPUT MODE (RCR.5 = 1). Figure ...
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Transmit Timing Diagrams Figure 19-5. Transmit Frame and Multiframe Timing FRAME TSYNC 2 TSYNC NOTE 1: TSYNC IN FRAME MODE (TCR.1 = 0). NOTE 2: TSYNC IN MULTIFRAME MODE (TCR.1 = 1). Figure ...
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Figure 19-7. Transmit Interleave Bus Operation TSYNC 1 TSER FR1 CH32 2 FR2 CH32 FR3 CH32 FR0 CH1 TSER SYSCLK 3 TSYNC FRAMER 3, CHANNEL 32 TSER NOTE 1: 4.096MHZ BUS CONFIGURATION. NOTE 2: 8.192MHZ BUS CONFIGURATION. NOTE 3: TSYNC ...
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Figure 19-8. Framer Synchronization Flowchart esync 1 Increm ent ync C ounter FAS R ...
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Figure 19-9. Transmit Data Flow TNAF.5-7 NOTES: 1. Auto Remote Alarm if enabled will only overwrite bit 3 of timeslot 0 in the Not Align Frames if the alarm needs to be sent. TSER TAF 1 0 Timeslot 0 Pass-Through ...
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... Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (T = 0°C to +70°C for DS21Q50L; -40°C to +85°C for DS21Q50LN.) A PARAMETER Logic 1 ...
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... AC TIMING PARAMETERS AND DIAGRAMS 21.1 Multiplexed Bus AC Characteristics AC CHARACTERISTICS—MULTIPLEXED PARALLEL PORT (V = 3.3V ±5 0°C to +70°C for DS21Q50L PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, DS High or RD Low Input Rise/Fall times R/W Hold Time R/W Setup Time before DS High ...
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Figure 21-1. Intel Bus Read AC Timing (PBTS = 0) ALE t ASD AD0–AD7 Figure 21-2. Intel Bus Write Timing (PBTS = 0) ALE t ASD AD0–AD7 t CYC PW ASH t ASED t ...
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Figure 21-3. Motorola Bus AC Timing (PBTS = ASD R/W AD0–AD7 (read) CS AD0–AD7 (write) PW ASH t ASED t RWS t t DDR ASL t AHL ASL t AHL 77 ...
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... Nonmultiplexed Bus AC Characteristics AC CHARACTERISTICS—NONMULTIPLEXED PARALLEL PORT (V = 3.3V ± 5 0°C to +70°C for DS21Q50L PARAMETER Setup Time for A0 to A7, Valid to CS Active Setup Time for CS Active to Either RD, WR Active Delay Time from Either Active to Data Valid Hold Time from Either RD, WR Inactive to ...
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Figure 21-4. Intel Bus Read Timing (PBTS = 0) A0–A7 D0– 0ns (min) RD Figure 21-5. Intel Bus Write Timing (PBTS = 0) A0–A7 D0– 0ns (min) WR Address Valid 5ns (min)/20ns (max) t1 0ns (min) ...
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Figure 21-6. Motorola Bus Read Timing (PBTS = 1) A0–A7 D0– 0ns (min) DS Figure 21-7. Motorola Bus Write Timing (PBTS = 1) A0–A7 D0– 0ns (min) DS Address Valid 5ns (min)/20ns (max) t1 ...
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... Serial Port AC CHARACTERISTICS—SERIAL PORT (BTS1 = 1, BTS0 = 3.3V ±5 0°C to +70°C for DS21Q50L PARAMETER Setup Time CS to SCLK Setup Time SDI to SCLK Hold Time SCLK to SDI SCLK High/Low Time SCLK Rise/Fall Time SCLK to CS Inactive CS Inactive Time SCLK to SDO Valid ...
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... Receive AC Characteristics AC CHARACTERISTICS—RECEIVER (V = 3.3.0V ±5 0°C to +70°C for DS21Q50L PARAMETER SYSCLK Period (Note 1) SYSCLK Pulse Width RSYNC Setup to SYSCLK Falling RSYNC Pulse Width Delay RCLK to RSER Valid Delay RCLK to RSYNC, OUTA, OUTB Delay SYSCLK to RSER Valid Delay SYSCLK to RSYNC, OUTA, OUTB Note 1: SYSCLK = 2 ...
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Figure 21-10. Receive AC Timing (Receive Elastic Store Enabled SYSCLK t D3 RSER 1 RSYNC 2 OUTA / OUTB 3 RSYNC NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR.5 = 0). NOTE 2: OUTA OR OUTB CONFIGURED ...
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... Transmit AC Characteristics AC CHARACTERISTICS—TRANSMIT (V = 3.3V ±5 0°C to +70°C for DS21Q50L PARAMETER TCLK Period TCLK Pulse Width TSYNC Setup to TCLK TSYNC Pulse Width TSER Setup to TCLK Falling TSER Hold from TCLK Falling TCLK Rise and Fall Times = 3.3V ± 5 -40°C to +85°C for DS21Q50LN.) ...
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Figure 21-11. Transmit AC Timing (IBO Disabled TCLK TSER 1 TSYNC 2 TSYNC OUTA/OUTB 3 NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR.0 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TCR.0 = 0). NOTE ...
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... Special Modes AC Characteristics AC CHARACTERISTICS—SPECIAL MODES (V = 3.3V ±5 0°C to +70°C for DS21Q50L PARAMETER RTIP Period RTIP Pulse Width RTIP Setup to RRING Falling TSER Hold from TCLK Falling RTIP, RRING Rise and Fall Times Special Mode: OUTBC Note: RTIP and RRING become NRZ data and clock inputs. ...
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