DS25MB100EVK National Semiconductor, DS25MB100EVK Datasheet

no-image

DS25MB100EVK

Manufacturer Part Number
DS25MB100EVK
Description
KIT EVAL FOR DS25MB100
Manufacturer
National Semiconductor
Datasheets

Specifications of DS25MB100EVK

Main Purpose
Interface, 2:1 Multiplexer
Utilized Ic / Part
DS25MB100
Lead Free Status / RoHS Status
Not applicable / Not applicable
Secondary Attributes
-
Embedded
-
Primary Attributes
-
© 2009 National Semiconductor Corporation
2.5 Gbps 2:1/1:2 CML Mux/Buffer with Transmit Pre-
Emphasis and Receive Equalization
General Description
The DS25MB100 is a signal conditioning 2:1 multiplexer and
1:2 fan-out buffer designed for use in backplane redundancy
or cable driving applications. Signal conditioning features in-
clude input equalization and programmable output Pre-em-
phasis that enable data communication in FR4 backplane up
to 2.5 Gbps. Each input stage has a fixed equalizer to reduce
ISI distortion from board traces. All output drivers have four
selectable levels of Pre-emphasis to compensate for trans-
mission losses from long FR4 backplane or cable attenuation
reducing deterministic jitter. The Pre-emphasis levels can be
independently controlled for the line-side and switch-side
drivers. The internal loopback paths from switch-side input to
switch-side output enable at-speed system testing. All receiv-
er inputs are internally terminated with 100Ω differential ter-
minating resistors. All driver outputs are internally terminated
with 50Ω to V
Functional Block Diagram
Note: All CML inputs and outputs must be AC coupled for optimal performance.
CC
.
202089
DS25MB100
Features
Applications
2:1 multiplexer and 1:2 buffer
0.25–2.5 Gbps fully differential data paths
Fixed input equalization
Programmable output Pre-emphasis
Independent Pre-emphasis controls
Programmable loopback modes
On-chip terminations
HBM ESD rating 6 kV on all pins
+3.3V supply
Low power, 0.45 W typical
Lead-less LLP-36 package
−40°C to +85°C operating temperature range
Backplane or cable driver
Redundancy and signal conditioning applications
CPRI/OBSAI
20208901
February 24, 2009
www.national.com

Related parts for DS25MB100EVK

DS25MB100EVK Summary of contents

Page 1

... All driver outputs are internally terminated with 50Ω Functional Block Diagram Note: All CML inputs and outputs must be AC coupled for optimal performance. © 2009 National Semiconductor Corporation DS25MB100 Features ■ 2:1 multiplexer and 1:2 buffer ■ 0.25–2.5 Gbps fully differential data paths ■ ...

Page 2

Simplified Block Diagram www.national.com 2 20208902 ...

Page 3

Pin Descriptions Pin Name Pin Number I/O LINE SIDE HIGH SPEED DIFFERENTIAL IO's IN Inverting and non-inverting differential inputs at the line side. IN+ and IN− have an internal 50Ω IN− 34 connected to an internal reference voltage. ...

Page 4

Connection Diagram Functional Description The DS25MB100 is a signal conditioning 2:1 multiplexer and a 1:2 buffer designed to support port redundancy up to 2.5 Gbps. The high speed inputs are self-biased to about 1.3V and are designed for AC coupling. ...

Page 5

Pre-Emphasis Level in mV DEL_[1:0] PP (VODB 1300 0 1 1300 1 0 1300 1 1 1300 (default) TABLE 4. Switch-Side Pre-Emphasis Controls Pre-Emphasis DES_[1:0] Level (VODB 1300 0 1 1300 1 0 ...

Page 6

... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage CML Input/Output Voltage Junction Temperature Storage Temperature Lead Temperature Soldering, 4 seconds Thermal Resistance, θ (Note 8) JA Thermal Resistance, θ ...

Page 7

Symbol Parameter T Pre-Emphasis Width Tested at −9 dB Pre-emphasis level, DEx[1:0]=11 PE x=S for switch side Pre-emphasis control x=L for line side Pre-emphasis control See Figure 4 on measurement condition. R Output Termination (Note On-chip termination from OUT+ or ...

Page 8

Note 4: K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000} K28.5 pattern is a 20-bit repeating pattern of +K28.5 and −K28.5 code groups {110000 0101 001111 1010} Note 5: Device output random jitter is a ...

Page 9

FIGURE 4. Test Condition for Output Pre-Emphasis Duration FIGURE 5. AC Test Circuit FIGURE 6. Receiver Input Termination and Bias Circuit 9 20208950 20208907 20208908 www.national.com ...

Page 10

Application Information www.national.com FIGURE 7. Application Diagram 10 20208909 ...

Page 11

FIGURE 8. Network Switch System With Redundancy 11 20208910 www.national.com ...

Page 12

Physical Dimensions www.national.com inches (millimeters) unless otherwise noted LLP-36 Package Order Number DS25MB100TSQ NS Package Number SQA36A 12 ...

Page 13

Notes 13 www.national.com ...

Page 14

... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...

Related keywords