ds2740 Maxim Integrated Products, Inc., ds2740 Datasheet
ds2740
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ds2740 Summary of contents
Page 1
... Range with External 10mΩ Sense Resistor (R ) SNS Analog Input Filter (IS1, IS2) Extends Dynamic Range for Pulse-Load Applications Current Accumulation Register Resolution 6.25μVhr (Both DS2740U and DS2740BU) 0.3125mAhr with External 20mΩ R SNS 0.6250mAhr with External 10mΩ R SNS ® ...
Page 2
... The interface can be operated with standard or overdrive timing. Although the DS2740 is primarily intended for location on the host system also suited for mounting in the battery pack. The DS2740 and FuelPack™ algorithms, along with host measurements of temperature and voltage, form a complete and accurate solution for estimating remaining capacity ...
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Figure 1. BLOCK DIAGRAM V DD 1-WIRE DQ INTERFACE AND ADDRESS SNS STATUS/CONTROL ACCUMULATED CURRENT CURRENT 15-Bit + Sign ADC Ω Ω IS2 IS1 R SNS PIO TIMEBASE ...
Page 4
... Figure 2. APPLICATION EXAMPLE 2.7V to 5.5V System Supply Battery Pack DATA PIO System GND DESCRIPTION or Positive 150 DQ DS2740 330 PIO SNS * * IS2 104 R SNS * 5.6V zener recommended for ESD protection when DATA or PIO contacts exposed, such as a removable battery pack application through a 10kΩ resistor to allow ...
Page 5
... Read and write access is allowed to all registers. PIO pin is active. In Sleep mode, the DS2740 operates in a low-power mode with no current measurement activity. Serial access to current, accumulated current, and status/control registers is allowed if V > ...
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... Every 1024th conversion, the ADC measures its input offset to facilitate offset correction. Offset correction occurs approximately once per hour in the DS2740U and four times per hour in the DS2740BU. The resulting correction factor is applied to the subsequent 1023 measurements. During the offset correction conversion, the ADC does not measure the IS1 to IS2 signal. A maximum error of ...
Page 7
... X SMOD SMOD —SLEEP Mode Enable. A value of 1 allows the DS2740 to enter Sleep mode when DQ is low for 2s. A value of 0 disables DQ related transitions to Sleep mode. The power-up default of SMOD = 0. RNAOP —Read Net Address Opcode. A value this bit sets the opcode for the Read Net Address command to 33h, while a 1 sets the opcode to 39h. The power-up default of RNAOP = 0. X — ...
Page 8
... Each DS2740 has a unique, factory-programmed 1-Wire net address that is 64 bits in length. The first eight bits are the 1-Wire family code (36h for DS2740). The next 48 bits are a unique serial number. The last eight bits are a cyclic redundancy check (CRC) of the first 56 bits (see Figure 7). The 64-bit net address and the 1-Wire I/O circuitry built into the device enable the DS2740 to communicate through the 1-Wire protocol detailed in the 1-Wire Bus System section of this data sheet ...
Page 9
... To facilitate this, each device attached to the 1-Wire bus must connect to the bus with open-drain or tri-state output drivers. The DS2740 uses an open-drain output driver as part of the bidirectional interface circuitry shown in Figure bidirectional pin is not available on the bus master, separate output and input pins can be connected together ...
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... Figure 10 presents a transaction flowchart of the net address commands. Read Net Address [33h or 39h]. This command allows the bus master to read the DS2740’s 1-Wire net address. This command can only be used if there is a single slave on the bus. If more than one slave is present, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result) ...
Page 11
... Skip Net Address [CCh]. This command saves time when there is only one DS2740 on the bus by allowing the bus master to issue a function command without specifying the address of the slave. If more than one slave device is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at the same time ...
Page 12
... COMMAND 55h NO F0h NO SEARCH YES YES DS2740 Tx BIT 0 DS2740 Tx BIT 0 MASTER Tx BIT 0 BIT BIT 0 MATCH ? YES YES DS2740 Tx BIT 1 DS2740 Tx BIT 1 MASTER Tx BIT 1 BIT BIT 1 MATCH ? YES YES DS2740 Tx BIT 63 DS2740 Tx BIT 63 MASTER Tx BIT CCh NO A5h NO SKIP ...
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... All of these types of signaling except the presence pulse are initiated by the bus master. The initialization sequence required to begin any communication with the DS2740 is shown in Figure 11. A presence pulse following a reset pulse indicates that the DS2740 is ready to accept a net address command. The bus master transmits (Tx) a reset pulse for t goes into Receive mode (Rx) ...
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... The bus master must keep the bus line low for at least 1 DS2740 to present valid data. The bus master can then sample the data t time slot. By the end of the read-time slot, the DS2740 releases the bus line and allows pulled high by the external pullup resistor. All read-time slots must be t recovery time between cycles ...
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... 2.0V PIO = V SS SLEEP V = 4.2V PIO = DS2740U I LSB DS2740BU I FS DS2740U (Note 2) OERR DS2740BU (Note 2) GERR q CA SAMP V = 3.5V at +25° ERR V (Note (Note (Note -0.3V to +6V -0.3V to +6V -40°C to +85°C -55°C to +125°C ...
Page 16
... Reset Time Low Presence Detect High Presence Detect Low All voltages are referenced to V Note 1: Offset performance requires proper circuit layout design free of surface contaminants. Note 2: The DS2740 enters the Sleep mode 2.0s to 2.4s after DQ goes low. Note 3: V (Note 4mA (Note 1) ...