DSP56F805FV80 Freescale Semiconductor, DSP56F805FV80 Datasheet

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Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F805 Rev. 16 09/2007 freescale.com ...

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Version History Rev. 16 Added revision history. Added this text to footnote any particular percent of the low pulse width.” Document Revision History Description of Change Table 3-8: “However, the high pulse width does not have to ...

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... GPIO 4 Memory & Dedicated Peripherals GPIO 14 * includes TCS pin which is reserved for factory use and is tied to VSS Freescale Semiconductor • Two 6-channel PWM Modules • Two 4-channel, 12-bit ADCs • Two Quadrature Decoders • CAN 2.0 B Module • Two Serial Communication Interfaces (SCIs) • ...

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... Fault inputs, fault tolerant design with dead time insertion; supports both center- and edge-aligned modes • Two 12-bit Analog-to-Digital Converters (ADC) which support two simultaneous conversions; ADC and PWM modules can be synchronized • Two Quadrature Decoders each with four inputs or two additional Quad Timers 4 56F805 Technical Data, Rev. 16 Freescale Semiconductor ...

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... The 56F805 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It also supports program execution from external memory (64K). Freescale Semiconductor 56F805 Technical Data, Rev. 16 56F805 Description ...

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... The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 6 56F805 Technical Data, Rev. 16 Freescale Semiconductor ...

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... Product Documentation The four documents listed in Table 2-1 56F805. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at www.freescale.com. Topic 56800E Detailed description of the 56800 family architecture, and Family Manual 16-bit core processor and the instruction set ...

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... Detailed Pins Description 9 Table 2-2 9 Table 2-3 3 Table 2-4 3 Table 2-5 16 Table 2-6 16 Table 2-7 4 Table 2-8 5 Table 2-9 14 Table 2-10 26 Table 2-11 4 Table 2-12 8 Table 2-13 4 Table 2-14 2 Table 2-15 9 Table 2-16 6 Table 2-17 6 Table 2-18 Freescale Semiconductor Table 2-1 ...

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... PHASEA1 (TB0) Quadrature PHASEB1 (TB1) Decoder1 or INDEX1 (TB2) Quad Timer B HOME1 (TB3) JTAG/OnCE™ Port * includes TCS pin which is reserved for factory use and is tied to VSS Figure 2-1 56F805 Signals Identified by Functional Group 1. Alternate pin functionality is shown in parenthesis. Freescale Semiconductor VCAPC ...

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... For more information, please refer to Section Input VPP—This pin should be left unconnected as an open circuit for normal functionality. 56F805 Technical Data, Rev. 16 for SS SS. Signal Description 5.2. Freescale Semiconductor ...

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... A8–A15 Output GPIOA0 Input/O – GPIOA7 utput Freescale Semiconductor Table 2-5 PLL and Clock State During Reset Input External Crystal Oscillator Input—This input should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Chip-driven Crystal Oscillator Output—This output should be connected to an 8MHz external crystal or ceramic resonator ...

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... When RD is deasserted high, the external data is latched inside the device. When RD is asserted, it qualifies the A0–A15, PS, and DS pins. RD can be connected directly to the OE pin of a Static RAM or ROM. 56F805 Technical Data, Rev. 16 Signal Description Signal Description Freescale Semiconductor ...

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... RESET Input (Schmitt) 1 RSTO Output 1 EXTBOOT Input (Schmitt) Freescale Semiconductor State During Signal Description Reset Input External Interrupt Request A—The IRQA input is a synchronized external interrupt request indicating an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. Input External Interrupt Request B—The IRQB input is an external interrupt request indicating an external device is requesting service ...

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... PWMB. Input FAULTB0 3—These four Fault input pins are used for – disabling selected PWMB outputs in cases where fault conditions originate off-chip. 56F805 Technical Data, Rev. 16 Signal Description Signal Description Freescale Semiconductor ...

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... SS Input GPIOE7 Input/ Output Freescale Semiconductor State During Reset Input SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected ...

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... TB0—Timer B Channel 0 Input Phase B—Quadrature Decoder #1 PHASEB input Input TB1—Timer B Channel 1 Input Index—Quadrature Decoder #1 INDEX input Input TB2—Timer B Channel 2 Input Home—Quadrature Decoder #1 HOME input Input TB3—Timer B Channel 3 56F805 Technical Data, Rev. 16 Signal Description Freescale Semiconductor ...

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... Type 1 MSCAN_ RX Input (Schmitt) 1 MSCAN_ TX Output Freescale Semiconductor State During Reset Input Transmit Data (TXD0)—SCI0 transmit data output Input Port E GPIO—This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCI output. ...

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... ADC channel 2 – Input VREF—Analog reference voltage for ADC. Must be set 0.3V for optimal performance. DDA State During Reset Input TC0 1—Timer C Channels 0 and 1 – Input TD0 3—Timer D Channels and 3 – 56F805 Technical Data, Rev. 16 Signal Description Signal Description Freescale Semiconductor ...

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... Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during Freescale Semiconductor State During Reset Input, pulled Test Clock Input— ...

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... V IN ΔV DD Δ PWM outputs Symbol Min V 3 3.0 DDA 56F805 Technical Data, Rev. 16 Min Max Unit V – – 0.3 0 0.3 0 – 0 0.3 V SSA DDA V – 0 3.0 V SSA SSA — Typ Max Unit 3.3 3.6 V 3.3 3.6 V Freescale Semiconductor ...

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... The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. Freescale Semiconductor Symbol Min Δ ...

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... IHPU I -210 — -50 ILPU I 20 — 180 IHPD I -1 — 1 ILPD , -10 — 10 OZL I -10 — 10 OZH I -15 — 15 IHA I -15 — 15 ILA V V – 0.7 — — Freescale Semiconductor Unit μA μA μA μA μA μA KΩ μA μA μA μA V ...

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... While power is ramping up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up rate is. The internally regulated voltage is typically 100mV less than V Freescale Semiconductor = 3.0– ...

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... Data Invalid state, when a signal level is in transition between V 24 IDD Analog IDD Total 20 40 Freq. (MHz) are tested using the V and and V for an input signal are shown Low – 56F805 Technical Data, Rev Figure 3-14) levels specified in the DC Characteristics High 90% 50% 10% Rise Time and Freescale Semiconductor 80 ...

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... Defines program cycle 6. Defines erase cycle 7. Defines mass erase cycle, erase whole block 8. Defines non-volatile store cycle Mode Read Word program Page erase Mass erase Freescale Semiconductor Data2 Valid Data2 Tri-stated Figure 3-3 Signal States Table 3-5 Flash Memory Truth Table ...

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... Figure 3-4, Figure 3-5, Figure 3-6 – us Figure 3-4, Figure 3-5 – us Figure 3-6 – us Figure 3-4 – us Figure 3-4, Figure 3-5, Figure 3-6 – ms Figure 3-4 – Figure 3-4 – Figure 3-4 – Figure 3-4 Freescale Semiconductor ...

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... XADR XE YADR YE DIN PROG Tnvs NVSTR IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR Freescale Semiconductor Tadh Tads Tprog Tpgs Thv Figure 3-4 Flash Program Cycle Terase Figure 3-5 Flash Erase Cycle 56F805 Technical Data, Rev. 16 Flash Memory Characteristics Tpgh Tnvh Trcv Tnvh ...

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... EXTAL) of 10pF to 13pF over temperature and process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF 28 Tme Figure 3-6 Flash Mass Erase Cycle Table 3-9. In 56F805 Technical Data, Rev. 16 Tnvh1 Trcv Figure 3-7 a recommended crystal Figure 3-8, no Freescale Semiconductor ...

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... As shown in Figure 3-7 no external load capacitors should be used. EXTAL XTAL Figure 3-8 Connecting a Ceramic Resonator Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators (which contain an internal bypass capacitor to ground). Freescale Semiconductor 9pF Recommended External Crystal R ...

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... XTAL EXTAL V External SS Clock SSA DD DDA Symbol Min osc t 6. – Figure 3-10 External Clock Timing 56F805 Technical Data, Rev. 16 Figure 3-9. The external clock 3 = 3.0–3.6V –40° to +85°C A Typ Max Unit — 80 MHz — — 90% 50% 10 Freescale Semiconductor ...

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... An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8MHz input crystal. 2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f User Manual. ZCLK = This is the minimum time required after the PLL set-up is changed to ensure reliable operation. Freescale Semiconductor Table 3-9 PLL Timing ...

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... L op Unit Min Max 6.5 — 7.5 — — — 4.2 4.8 — 2.2 — — 0 — — 18.7 0 — 19 — — — 1 — (T*WS)+1 -4.4 — — 2.4 — (T*WS) + 2.4 6.8 — 0 — 14.1 — 12.8 — Freescale Semiconductor ...

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... Memory Access Time = (Top*WS) + (Top- 11.5) A0–A15, PS, DS (See Note AWR t WRWR WR t WRD D0–D15 Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 3-11 External Bus Asynchronous Timing Freescale Semiconductor t ARDD t ARDA t WRRD DOS DOH Data Out 56F805 Technical Data, Rev ...

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... Figure 3-12 — ns Figure 3-13 — ns Figure 3-14 — ns Figure 3-14 — ns Figure 3-15 2T — ns Figure 3-16 Figure 3-16 — 275,000T ns — 12T ns Figure 3-17 — 275,000T ns — 12T ns Figure 3-17 — 275,000T ns — 12T ns Figure 3- Freescale Semiconductor ...

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... IDM IRQA, IRQB Purpose I/O Pin t IG IRQA, IRQB Figure 3-14 External Level-Sensitive Interrupt Timing Freescale Semiconductor Reset, Stop, Wait, Mode Select, and Interrupt Timing IRW First Interrupt Instruction Execution a) First Interrupt Instruction Execution b) General Purpose I/O 56F805 Technical Data, Rev. 16 ...

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... Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service RSTO 36 t IRI IRQ RSTO Figure 3-18 Reset Output Timing 56F805 Technical Data, Rev. 16 First Interrupt Vector Instruction Fetch First Instruction Fetch Not IRQA Interrupt Vector First IRQA Interrupt Instruction Fetch Freescale Semiconductor ...

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... Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave 1. Parameters listed are guaranteed by design. Freescale Semiconductor Table 3-12 SPI Timing = 3.0–3 SSA DD DDA Symbol Min ELD ...

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... Figure 3-20 SPI Master Timing (CPHA = held High on master MSB in Bits 14– Master MSB out Bits 14– held High on master MSB in Bits 14– Master MSB out Bits 14– 56F805 Technical Data, Rev LSB in (ref Master LSB out LSB Master LSB out t R Freescale Semiconductor ...

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... SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 3-21 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input MISO (Output) t MOSI (Input) Figure 3-22 SPI Slave Timing (CPHA = 1) Freescale Semiconductor ELD Slave MSB out Bits 14– MSB in Bits 14– ...

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... DDA A Symbol Min P 8T+ 4T 2T+3 PH 56F805 Technical Data, Rev ≤ = –40° to +85°C, C 50pF 80MHz Max Unit — ns — ns — ns — INHL P OUTHL –40° to +85°C, C < 50pF 80MHz L OP Max Unit — ns — ns — 0V 3.0–3.6V Freescale Semiconductor ...

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... MHz. MAX 2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. 4. Parameters listed are guaranteed by design. RXD SCI receive data pin (Input) Freescale Semiconductor ...

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... Technical Data, Rev. 16 Typ Max Unit — REF — 12 Bits +/-2.5 +/-4 4 LSB +/- 0.9 +/-1 4 LSB — 5 MHz — DDA 6 — t cycles AIC 1 — t cycles AIC 5 — 1.00 1.10 — -15 + — — — bit 70 — dB 100 — KHz Freescale Semiconductor 6 6 ...

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... The number 5 microseconds originates from the fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1Mbps. 2. Parameters listed are guaranteed by design. Freescale Semiconductor Symbol Min I — ...

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... Table 3-18 JTAG Timing = 3.0–3 SSA DD DDA Symbol TRST )/2 56F805 Technical Data, Rev ≤ = –40° to +85°C, C 50pF 80MHz Min Max DC 10 100 — 50 — 0.4 — 1.2 — — 26.6 — 23.5 50 — 4T — Freescale Semiconductor Unit MHz ...

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... TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 3-30 Test Access Port Timing Diagram TRST (Input) DE Freescale Semiconductor t DS Input Data Valid TRST Figure 3-31 TRST Timing Diagram t DE Figure 3-32 OnCE—Debug Event 56F805 Technical Data, Rev. 16 ...

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... Technical Data, Rev. 16 ANA3 ANA2 Pin 73 ANA1 ANA0 V REF FAULTA3 FAULTA2 MSCAN_RX FAULTA1 MSCAN_TX FAULTA0 RXD1 ISA2 V SS ISA1 V DD ISA0 VCAPC TRST TDO TXD1 TDI TC1 TMS TC0 TCK FAULTB3 TCS FAULTB2 IRQB IRQA RD WR Pin A15 A14 Freescale Semiconductor ...

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... PWMB3 PWMB4 PWMB5 ISB0 ISB1 ISB2 63 28 A10 64 29 FAULTB0 65 30 A11 66 Freescale Semiconductor Pin Signal Name Signal Name No. A14 73 ANA4 A15 74 ANA5 V 75 ANA6 ANA7 RD 77 XTAL IRQA 78 EXTAL IRQB 79 V SSA FAULTB2 80 V DDA TCS FAULTB3 TCK TC0 84 GPIOB0 ...

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... A12 68 33 A13 Pin Signal Name Signal Name No. FAULTA3 103 PWMA3 VREF 104 GPIOD2 ANA0 105 PWMA4 ANA1 106 PWMA5 ANA2 107 TXD0 ANA3 108 RXD0 56F805 Technical Data, Rev. 16 Pin Signal Name No. 139 D4 140 D5 141 D6 142 D7 143 D8 144 D9 Freescale Semiconductor ...

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... Figure 4-2 144-pin LQFP Mechanical Information Please see www.freescale.com for the most current case outline. Freescale Semiconductor 56F805 Technical Data, Rev. 16 Package and Pin-Out Information 56F805 49 ...

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... Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance °C can be obtained from the equation × θ θJC θCA . For example, the user can change the air flow around θCA 56F805 Technical Data, Rev not satisfactorily answer whether θJA Freescale Semiconductor ...

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... Ensure that capacitor leads and associated printed circuit traces that connect to the chip V are less than 0.5 inch per capacitor lead. • Bypass the V and capacitor such as a tantalum capacitor. Freescale Semiconductor – T )/P where CAUTION pin. /V Ceramic and tantalum capacitors tend to provide better performance DDA SSA ...

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... TRST must be externally asserted even when the user relies on the internal power on reset for functional test purposes. • Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming and V REF DDA 56F805 Technical Data, Rev. 16 pins. SSA Freescale Semiconductor ...

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... Low Profile Plastic Quad Flat Pack (LQFP) 56F805 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) *This package is RoHS compliant. Freescale Semiconductor Pin Package Type Count 144 144 56F805 Technical Data, Rev. 16 Electrical Design Considerations Ambient Frequency Order Number (MHz) 80 DSP56F805FV80 80 DSP56F805FV80E* 53 ...

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... Technical Data, Rev. 16 Freescale Semiconductor ...

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... Freescale Semiconductor 56F805 Technical Data, Rev. 16 Electrical Design Considerations 55 ...

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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® ...