el4511 Intersil Corporation, el4511 Datasheet

no-image

el4511

Manufacturer Part Number
el4511
Description
Super Sync Separator
Manufacturer
Intersil Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
el4511CS
Manufacturer:
INTERSIL
Quantity:
20 000
Part Number:
el4511CU
Manufacturer:
INTERSIL
Quantity:
587
Part Number:
el4511CU
Manufacturer:
INTERSIL
Quantity:
20 000
Part Number:
el4511CUZ
Manufacturer:
Intersil
Quantity:
873
Part Number:
el4511CUZ
Manufacturer:
Intersil
Quantity:
3 500
Part Number:
el4511CUZ
Manufacturer:
EL
Quantity:
20 000
Part Number:
el4511CUZ-T
Manufacturer:
INTERSIL
Quantity:
20 000
Part Number:
el4511ICUZ
Manufacturer:
INTERSIL
Quantity:
20 000
Super Sync Separator
The EL4511 sync separator IC is designed for operation in
the next generation of DTV, HDTV, and projector
applications, as well as broadcast equipment and other
applications where video signals need to be processed.
The EL4511 accepts sync on green, separate sync, and H/V
sync inputs, automatically selecting the relevant format. It is
also capable of detecting and decoding tri-level syncs used
with the latest HD systems. Unlike standard sync separators,
the EL4511 can automatically detect the line rate and locks
to it, without the use of an external R
The EL4511 is available in a 24-pin QSOP package and
operates over the full 0°C to 70°C temperature range.
Ordering Information
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
EL4511CU
EL4511CU-T7
EL4511CU-T13
EL4511CUZ
(See Note)
EL4511CUZ-T7
(See Note)
EL4511CUZ-T13
(See Note)
NUMBER
PART
24-Pin QSOP
24-Pin QSOP
24-Pin QSOP
24-Pin QSOP
24-Pin QSOP
24-Pin QSOP
PACKAGE
(Pb-Free)
(Pb-Free)
(Pb-Free)
®
1
Copyright © Intersil Americas Inc. 2002-2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
TAPE &
Data Sheet
REEL
SET
13”
13”
7”
7”
-
-
resistor.
PKG. DWG. #
MDP0040
MDP0040
MDP0040
MDP0040
MDP0040
MDP0040
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Composite, component, HDTV, and PC signal-compatible
• Tri-level & bi-level sync-compatible
• Auto sync detection
• 150kHz max line rate
• Low power
• Small package outline
• 3.3V and 5V operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• HDTV/DTV analog inputs
• Video projectors
• Computer monitors
• Set top boxes
• Security video
• Broadcast video equipment
Pinout
July 21, 2005
SYNCLOCK
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
VBLANK
SYNCIN
VERTIN
SDENB
GNDD1
LEVEL
PDWN
Manufactured under License, U.S. Patents 5,486,869; 5,754,250
XTAL
SDA
SCL
HIN
10
11
12
1
2
3
4
5
6
7
8
9
(24-PIN QSOP)
TOP VIEW
EL4511
Manufactured under U.S. Patent 5,528,303
24
23
22
21
20
19
18
17
16
15
14
13
XTALN
ODD/EVEN
VERTOUT
HOUT
BACKPORCH
SYNCOUT
VCCD
GNDD2
GNDA2
VCCA2
VCCA1
GNDA1
EL4511
FN7009.7

Related parts for el4511

el4511 Summary of contents

Page 1

... Data Sheet Super Sync Separator The EL4511 sync separator IC is designed for operation in the next generation of DTV, HDTV, and projector applications, as well as broadcast equipment and other applications where video signals need to be processed. The EL4511 accepts sync on green, separate sync, and H/V sync inputs, automatically selecting the relevant format ...

Page 2

... SYNCOUT Td BACKPORCH Timing Relative to BACKPORCH Input LEVEL OUTPUT DRIVER, LEVEL Amplitude of V LEVEL SYNC Z O/P Resistance of Driver Stage LEVEL 2 EL4511 = 25°C) to GND) +6V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C S +0.3V Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C S Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70° ...

Page 3

... T Clock to Data Out Time CD NOTES: 1. NTSC signal; see curves for other rates. 2. XTAL pin must be low, otherwise 70µA. 3. I/P range reduces 3.3V - 4.5V (see Timing Diagram 1 EL4511 = +5V 25°C, NTSC input signal on SYNCIN, no output loads, unless CCA1 CCA2 CCD A CONDITIONS Refer to description of operation ...

Page 4

... PIN TYPE Input Crystal input (see Table 2 for details) Logic Output Vertical blank output Logic Output Indicates that the EL4511 has locked to the line rate and has found three consecutive “good H lines” Logic Input Power-down = hi Logic Input Serial interface enable = low ...

Page 5

... HORIZONTAL SYNC HIN PROCESSING POWER DOWN PDWN LOW ACTIVE SERIAL SDENB DATA ENABLE SERIAL CLOCK SCL SERIAL I/F SERIAL DATA SDA GNDA1 5 EL4511 VCCD & DIGITAL PROCESSING RESET RATE REFERENCE ACQUISITION OSCILLATOR OSCILLATOR VCCA2 GNDA2 XTALIN MODE CONTROL PINS FIGURE 3. BLOCK DIAGRAM ...

Page 6

... Odd-even output is low for even field, and high for odd field. e. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). 6 EL4511 ...

Page 7

... Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). 7 EL4511 START OF FIELD ONE 624 625 ...

Page 8

... BLANK ODD/EVEN SYNCIN 560 561 562 SYNCOUT H OUT BACKPORCH V OUT V BLANK ODD/EVEN FIGURE 6. EXAMPLE OF HDTV 1080I/30 LINE COMPOSITE VIDEO: INTERLACED, ODD & EVEN FIELD 8 EL4511 DEFAULT 20 LINES ODD FIELD 563 564 565 566 567 DEFAULT 20 LINES EVEN FIELD ... ...

Page 9

... FIGURE 7. HDTV 1080I/25 LINE COMPOSITE VIDEO: INTERLACED ODD & EVEN FIELD (1250 LINES) 9 EL4511 Default 20 Lines Default 20 Lines FN7009.7 July 21, 2005 ...

Page 10

... HOUT Timing Relative to Input HOUT td BACKPORCH Timing Relative to Input BACKPORCH T Horizontal Output Width HOUT T BACKPORCH (Clamp) Width BACKPORCH NOTE: 1. Delay variation is less than 2.5ns over temperature range. 10 EL4511 = V = +5V 25°C, NO FILTER (REGISTER 2 BIT CCD A COLOR BURST V SLICE 50% V SYNC (SYNC TIP SYNC ...

Page 11

... HOUT Timing Relative to Input HOUT td BACKPORCH Timing Relative to Input BACKPORCH T Horizontal Output Width HOUT T BACKPORCH (Clamp) Width BACKPORCH NOTE: 1. Delay variation is less than 2.5ns over temperature range. 11 EL4511 = V = +5V 25°C, FILTER IN (REGISTER 2 BIT CCD A COLOR BURST V SLICE 50% V SYNC (SYNC TIP SYNC ...

Page 12

... HOUT Timing Relative to Input HOUT td BACKPORCH Timing Relative to Input BACKPORCH T Horizontal Output Width HOUT T BACKPORCH (Clamp) Width BACKPORCH NOTE: 1. Delay variation is less than 2.5ns over temperature range. 12 EL4511 = V = +3.3V/+5V 25°C, NO FILTER (REGISTER 2 BIT CCD A td HOUT T HOUT td BACKPORCH CONDITIONS See Timing Diagram 3 ...

Page 13

... HOUT Timing Relative to Input HOUT td BACKPORCH Timing Relative to Input BACKPORCH T Horizontal Output Width HOUT T BACKPORCH (Clamp) Width BACKPORCH NOTE: 1. Delay variation is less than 2.5ns over temperature range. 13 EL4511 = V = +3.3V/+5V 25°C, FILTER (REGISTER 2 BIT CCD A td HOUT T HOUT td BACKPORCH CONDITIONS See Timing Diagram 4 ...

Page 14

Operation Summarized Table Default register settings. All with no external analog filter. No Mode setting. 525/625 PINS 1 & DIGITAL OPERATING 24 XTAL, FILTER STANDARD DEFAULT XTALN ENABLED SDTV (Clean signals) 525 NTSC Yes 00 default 625 PAL Yes 00 ...

Page 15

Operation Summarized Table Default register settings. All with no external analog filter. No Mode setting. 525/625 (Continued) PINS 1 & DIGITAL OPERATING 24 XTAL, FILTER STANDARD DEFAULT XTALN ENABLED 1080 I / (29/30) Yes 00 default 1080 I / (48/50) ...

Page 16

... HIN input at a TTL level. The EL4511 will continue to monitor these two signals in turn until an appropriate signal is detected. If only one of HIN and SYNCIN is enabled, the EL4511 will continuously monitor the selected signal until an appropriate signal is detected; this will give a shorter lock time where only one type of signal is used ...

Page 17

... If the vertical sync input pin, VERTIN, is enabled, the EL4511 will automatically detect whether a valid signal is present on that pin, and incorporate that signal into the algorithm. ...

Page 18

... By default, the EL4511 will wake up with Register 9, bit 6 set to Low. This will allow the use of logic levels on pins 1 & drive register1, bits 5:3 and register 2 bit 0 into the combinations shown in Table 2 ...

Page 19

... As there is no Microcontroller connected in this example, there is no need for a XTAL at pins 1 & 24. These pins can be used to force the EL4511 to select the correct operation (and speed up acquisition). Note that a Low Pas Filter is in the NTSC/PAL signal path to reduce noise, glitches and subcarrier. (In signals with bad Croma/Luma gain balance, the subcarrier can extend into the sync slicing level) (See Table 2 for details ...

Page 20

... XTALN (PIN 24) FIGURE 10. BLOCK DIAGRAM OF REFERENCE OSCILLATOR 20 EL4511 Example: Using a 32.768kHz crystal, the count period is 30.52µs. With a 20ms vertical rate, there will be approximately 656 cycles (290 Hex) in the "counts per field" registers 13 and 14. With a 16.666'ms vertical rate, the count of 546 (222 Hex) will be seen. Computer & ...

Page 21

... EnTriLevel, EnBiLevel and EnHinVin; these enable tri-level sync detection, two-level sync detection and separate H/V (VGA) sync detection, respectively. Other signals used to prioritize tri-level syncs (TriLevPriority), separate H/V (Hin Priority only allow signals from HIN/VERTIN (HinVinOnly). 21 EL4511 Hin HinVin REGISTER Priority Only 0 ...

Page 22

... Number of lines before vertical sync time. 1 HIN polarity on reset if EnHpolarityDet = Lo. 1 VERTIN polarity on reset and if EnVpolarityDet = Lo. 1 Allows EL4511 to detect and set polarity on HIN. 1 Allows EL4511 to detect and set polarity on VERTIN. R/W 22h 0 Multiplexes clock onto V R Only valid if V circuit is enabled ...

Page 23

... VinSyncDet 1 VinPolarity 0 HPolarity 16 Oscillator Settings Observe 2 4 RateLocked 3 ALOS WRITE TO REGISTER OF EL4511 (WRITE INDICATED WITH ADDRESS = 0XXXXXXX) SDENB t(SCL)HI t(SCL)LO SCL SDA 0 td(SCL) START “0”=WRITE REGISTER ADDRESS 7 BITS READ FROM REGISTER OF EL4511 (READ INDICATED WITH ADDRESS = 1XXXXXXX) SDENB t(SCL)HI t(SCL)LO ...

Page 24

... As some of the signals in this application were non standard formats, the fixed slice mode is used by setting register 2, bit high. Register 1, bit 6 is also set to a high. This forced the EL4511 to provide outputs even when the input signals are not recognized by the internal algorithms. VIDEO SIGNALS (RGB) 75Ω ...

Related keywords