EL5126 INTERSIL [Intersil Corporation], EL5126 Datasheet
EL5126
Related parts for EL5126
EL5126 Summary of contents
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... The EL5126 has 8 outputs and is available in a 32-pin LPP package specified for operation over the full -40°C to +85°C temperature range. Ordering Information ...
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... Input Resistance SDIN DIN t Setup Time S t Hold Time H t Rise Time R t Fall Time F 2 EL5126 = 25°C) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves = 5V 13V 2V REFH REFL CONDITION ...
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... INPUT CODE FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE 3 EL5126 PIN TYPE Power Positive power supply for analog circuits Power Positive power supply for digital circuits Analog Input High reference voltage Analog Input Low reference voltage Power Ground Analog Decoupling capacitor for internal reference generator ...
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... C =4.7nF L R =20Ω =180pF L FIGURE 5. TRANSIENT LOAD REGULATION (SINKING) M=400µs/DIV FIGURE 7. LARGE SIGNAL RESPONSE (FALLING FROM 8V TO 0V) 4 EL5126 (Continued) 0mA 5mA 5V 4.4 4.5 4.8 5 FIGURE 4. TRANSIENT LOAD REGULATION (SOURCING) FIGURE 6. LARGE SIGNAL RESPONSE (RISING FROM 0V SCLK SDA OUTPUT FIGURE 8. SMALL SIGNAL RESPONSE (RISING FROM 0V ...
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... Each of the eight reference voltage outputs can be set with a 10-bit resolution. These outputs can be driven to within 50mV of the power rails of the EL5126. As all of the output buffers are identical also possible to use the EL5126 for applications other than LCDs where multiple voltage references are required that can be set to 10 bit accuracy ...
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... Device Address and write/read bit. This address bit long device address and only two device addresses (74H and 75H) are allowed for the EL5126. The first 6 bits (A6 to A1, MSBs) of the device address have been factory programmed and are always 111010. Only the least significant bit A0 is allowed to change the logic state, which can be tied to VSD or DGND ...
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I C Timing Diagram 1 STANDARD MODE (STD/REG = HIGH) WRITE MODE Start Device Address W A Data Data CLK In 1 ...
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... STOP CONDITION CLOCK OSCILLATOR The EL5126 requires an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn’t be changed at the rising edges of the OSC clock ...
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... This means that a large change of 16V can take between 3ms and 3.4ms depending on the absolute timing relative to the update cycle. 9 EL5126 EIGHT VOLTAGE CHANNEL SOURCES MEMORY ...
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... A low impedance and clean analog ground i plane should be used for the EL5126. The traces from the two ground pins to the ground plane must be very short. The thermal pad of the EL5126 should be connected to the analog ground plane. Lead length should be as short as possible and all power supply pins must be well bypassed. A 0.1µ ...
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... OUTA OSC +5V OSC_SEL +12V VS OUTB 0.1µF OUTC +5V VSD 0.1µF FILTER OUTD DATA IN SDA CLOCK SCL OUTE CAP 0.1µF OUTF LOW REFERENCE VOLTAGE REFL 0.1µF OUT STD GND OUTH EL5126 COLUMN (SOURCE) DRIVER LCD PANEL ADDRESS = H74 ADDRESS = H75 ...