ep2sgx60e Altera Corporation, ep2sgx60e Datasheet

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... Altera Corporation May 2008 4. Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet 1-, 4-, 16-, 64-, and 128-Mbit flash memory devices that serially ® configure Stratix III, Stratix II GX, and Stratix II FPGAs, Arria™ GX ® ...

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... Memory Size (Bits) 1,048,576 4,194,304 16,777,216 67,108,864 134,217,728 EPCS16 EPCS64 EPCS128 ( ( — — — (2) v — — — — Altera Corporation May 2008 ...

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... EPCS16, EPCS64, or EPCS128. Table 4–3. Serial Configuration Device Support for Stratix II GX Devices Raw Binary File Size Stratix II GX Device (Bits) EP2SGX30C 9,640,672 EP2SGX30D EP2SGX60C 16,951,824 EP2SGX60D EP2SGX60E EP2SGX90E 25,699,104 EP2SGX90F EP2SGX130G 37,325,760 Notes to Table 4–3: (1) These are uncompressed file sizes. ...

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... Serial Configuration Device EPCS16 EPCS64 EPCS128 ( ( — — EPCS16 EPCS64 EPCS128 ( ( — Altera Corporation May 2008 ...

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... EP2C50 9,951,104 EP2C70 14,319,216 Notes to Table 4–7: (1) These are uncompressed file sizes. (2) This is with the Cyclone II compression feature enabled. Altera Corporation May 2008 lists the serial configuration device used with each Cyclone III Serial Configuration Device (1) EPCS1 EPCS4 v — v — v — ...

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... Configuration Handbook, Volume 2 lists the serial configuration device used with each Cyclone Serial Configuration Device (1) EPCS1 EPCS4 (2) v — v — Serial configuration devices cannot be cascaded. EPCS16 EPCS64 EPCS128 Altera Corporation May 2008 ...

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... With this core, you can create a system with a Nios embedded processor that allows software access to any memory location within the serial configuration device. f For more information about accessing memory within the serial configuration device, refer to the Altera Corporation May 2008 shows the serial configuration device block diagram. Control Logic I/O Shift ...

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... FPGA in AS configuration mode. 4–8 Configuration Handbook, Volume 2 Stratix III Stratix II GX Stratix II Arria GX Cyclone series FPGAs This section is only relevant for FPGAs that support the AS configuration scheme. Figure 4–3 Figure 4–2 shows a shows a serial configuration Altera Corporation May 2008 ...

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... Connect the FPGA MSEL[] input pins to select the AS configuration mode. For details, refer to the appropriate (3) FPGA family chapter in the Configuration Handbook. (4) For more information about configuration pin I/O requirements scheme for a Cyclone III FPGA, refer to the Configuring Cyclone III Devices Altera Corporation May 2008 (1) ( ...

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... Configuration Handbook, Volume 2 (1) V ( CONF_DONE nSTATUS nCONFIG nCE DATA0 DCLK nCSO ASDO chapter in volume 1 of the Cyclone III Device Handbook. Figures 4–2 and 4–3). Subsequently, the FPGA sends the Cyclone FPGA nCEO N.C. 00 MSEL[1..0] (3) Altera Corporation May 2008 ...

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... Connect the FPGA MSEL[] input pins to select the PS configuration mode. For details, refer to the appropriate (4) FPGA family chapter in the Configuration Handbook. (5) For more information about configuration pin I/O requirements scheme for a Cyclone III FPGA, refer to the Configuring Cyclone III Devices Altera Corporation May 2008 Note (5) (1) (1) (1) V ...

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... EPCS4 EPCS1 524,288 bytes 131,072 bytes (4 Mbits) (1 Mbit 65,536 bytes 32,768 bytes (512 Kbits) (256 Kbits) 256 128 2,048 512 256 bytes 256 bytes End H'FFFFFF H'FBFFFF H'F7FFFF H'F3FFFF H'EFFFFF H'EBFFFF H'E7FFFF H'E3FFFF H'DFFFFF H'DBFFFF Altera Corporation May 2008 ...

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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet Table 4–10. Address Range for Sectors in EPCS128 (Part Altera Corporation May 2008 Address Range (Byte Addresses in HEX) Sector Start H'D40000 53 H'D00000 52 H'CC0000 51 H'C80000 50 H'C40000 49 H'C00000 48 H'BC0000 47 H'B80000 46 H'B40000 45 H'B00000 ...

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... H'7E0000 126 H'7D0000 125 H'7C0000 124 H'7B0000 123 End H'57FFFF H'53FFFF H'4FFFFF H'4BFFFF H'47FFFF H'43FFFF H'3FFFFF H'3BFFFF H'37FFFF H'33FFFF H'2FFFFF H'2BFFFF H'27FFFF H'23FFFF H'1FFFFF H'1BFFFF H'17FFFF H'13FFFF H'0FFFFF H'0BFFFF H'07FFFF H'03FFFF End H'7FFFFF H'7EFFFF H'7DFFFF H'7CFFFF H'7BFFFF Altera Corporation May 2008 ...

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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet Table 4–11. Address Range for Sectors in EPCS64 (Part Altera Corporation May 2008 Address Range (Byte Addresses in HEX) Sector Start H'7A0000 122 H'790000 121 H'780000 120 H'770000 119 H'760000 118 ...

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... H'3E0000 62 H'3D0000 61 H'3C0000 60 H'3B0000 59 End H'5AFFFF H'59FFFF H'58FFFF H'57FFFF H'56FFFF H'55FFFF H'54FFFF H'53FFFF H'52FFFF H'51FFFF H'50FFFF H'4FFFFF H'4EFFFF H'4DFFFF H'4CFFFF H'4BFFFF H'4AFFFF H'49FFFF H'48FFFF H'47FFFF H'46FFFF H'45FFFF H'44FFFF H'43FFFF H'42FFFF H'41FFFF H'40FFFF H'3FFFFF H'3EFFFF H'3DFFFF H'3CFFFF H'3BFFFF Altera Corporation May 2008 ...

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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet Table 4–11. Address Range for Sectors in EPCS64 (Part Altera Corporation May 2008 Address Range (Byte Addresses in HEX) Sector Start H'3A0000 58 H'390000 57 H'380000 56 H'370000 55 H'360000 54 H'350000 53 H'340000 52 H'330000 51 H'320000 50 H'310000 ...

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... H'080000 8 H'070000 7 H'060000 6 H'050000 5 H'040000 4 H'030000 3 H'020000 2 H'010000 1 H'000000 0 End H'1AFFFF H'19FFFF H'18FFFF H'17FFFF H'16FFFF H'15FFFF H'14FFFF H'13FFFF H'12FFFF H'11FFFF H'10FFFF H'0FFFFF H'0EFFFF H'0DFFFF H'0CFFFF H'0BFFFF H'0AFFFF H'09FFFF H'08FFFF H'07FFFF H'06FFFF H'05FFFF H'04FFFF H'03FFFF H'02FFFF H'01FFFF H'00FFFF Altera Corporation May 2008 ...

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... Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet Table 4–12. Address Range for Sectors in EPCS16 Altera Corporation May 2008 Address Range (Byte Addresses in HEX) Sector Start H'1F0000 31 H'1E0000 30 H'1D0000 29 H'1C0000 28 H'1B0000 27 H'1A0000 26 H'190000 25 H'180000 24 H'170000 23 H'160000 22 H'150000 21 H'140000 ...

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... Address Range (Byte Addresses in HEX) Sector Start H'70000 7 H'60000 6 H'50000 5 H'40000 4 H'30000 3 H'20000 2 H'10000 1 H'00000 0 Address Range (Byte Addresses in HEX) Sector Start H'18000 3 H'10000 2 H'08000 1 H'00000 0 End H'7FFFF H'6FFFF H'5FFFF H'4FFFF H'3FFFF H'2FFFF H'1FFFF H'0FFFF End H'1FFFF H'17FFF H'0FFFF H'07FFF Altera Corporation May 2008 ...

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... Read silicon ID operation is available only for EPCS1, EPCS4, EPCS16, and EPCS64. (5) Read Device Identification operation is available only for EPCS128. Altera Corporation May 2008 shows the operation sequence for every operation (1) Address Bytes ...

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... High Impedance Power up Write bytes operation completion Write status operation completion Erase bulk operation completion Erase sector operation completion shows the timing diagram for the write disable operation Operation Code Altera Corporation May 2008 ...

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... The read status operation code is b'0000 0101, with the MSB listed first. You can use the read status operation to read the status register. Figures 4–7 serial configuration devices. Figure 4–7. EPCS4, EPCS16, EPCS64, and EPCS128 Status Register Status Bits Figure 4–8. EPCS1 Status Register Status Bits Altera Corporation May 2008 ...

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... Table 4–16 Memory Content Unprotected Area All four sectors Three sectors Two sectors: 0 and 1 None Memory Content Unprotected Area All eight sectors Seven sectors Six sectors Four sectors None None None None Altera Corporation May 2008 ...

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... Upper half (64 sectors 127 All sectors (128 sectors 127) Altera Corporation May 2008 Memory Content Protected Area All sectors (32 sectors 0 to 31) Lower 31/32nds (31 sectors 30) Lower 15/16ths (30 sectors 29) Lower seven-eighths (28 sectors 27) Lower three-quarters (24 sectors 23) ...

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... Lower half (32 sectors 31) None Figure 4– Status Register Out MSB Table 4–16 through Unprotected Area 15 Status Register Out MSB Table 4–20. After setting the Altera Corporation May 2008 ...

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... DATA pin, beginning with the MSB. For reading Raw Programming Data files (.rpd), the content is shifted out serially beginning with the LSB. Each data bit is shifted out on the falling edge of Altera Corporation May 2008 Figure 4–10 in Table 4– ...

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... Configuration Handbook, Volume 2 Figure 4–11 shows the timing diagram for the read bytes 24-Bit Address ( MSB DATA Out 1 DATA Out MSB (2) Altera Corporation May 2008 ...

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... DATA output pin. If this operation is shifted in during an erase or write cycle ignored and has no effect on the cycle that is in progress. shows the serial configuration device identification. Altera Corporation May 2008 shows the serial configuration device silicon IDs. Serial Configuration Device ...

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... Dummy Byte 1 Dummy Byte MSB Figure 4–14. Silicon ID (Binary Value) b'0001 1000 Figure 4–13. The device can Note ( Silicon MSB Altera Corporation May 2008 31 ...

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... The erase bulk operation sets all memory bits 0xFF. Similar to the write bytes operation, the write enable operation must be executed prior to the erase bulk operation so that the write enable latch bit in the status register is set to 1. Altera Corporation May 2008 in Table 4–23 ...

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... Figure 4–15 shows the timing diagram. in Table 4–23 EB nCS DCLK Operation Code ASDI through 4–14 for sector address range information.) Drive Figure 4–16 shows the timing diagram. for the self-timed erase bulk cycle Altera Corporation May 2008 ...

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... The serial configuration device then goes into stand-by power mode. The I parameter specifies the V power mode and the stand-by power mode (refer to Altera Corporation May 2008 in Table 4– ...

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... After an error, configuration automatically restarts if the Auto-Restart Upon Frame Error option is turned on in the Quartus II software. If the option is turned off, the system must monitor the nSTATUS signal for errors and then pulse the nCONFIG signal low to restart configuration. 4–34 Configuration Handbook, Volume 2 Altera Corporation May 2008 ...

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... CSH (1) t Write bytes cycle time for EPCS1, EPCS4, WB EPCS16, and EPCS64 Write bytes cycle time for EPCS128 (1) t Write status cycle time WS Altera Corporation May 2008 shows the timing waveform for write operation to the serial Bit n 1 defines the serial configuration device timing parameters for ...

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... DCLK low time Min Typ Max — — — — 68 160 — 105 250 — — ODIS Bit 0 Min Max — 20 MHz 25 — 25 — Altera Corporation May 2008 Unit Unit ns ns ...

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... DCLK frequency from Stratix II or Cyclone II FPGA (20 MHz) DCLK frequency from Cyclone III FPGA DCLK frequency from Stratix III FPGA Altera Corporation May 2008 Symbol Parameter Output disable time after read Clock falling edge to data shows the timing waveform for FPGA AS configuration ...

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... Quartus II software. In addition, many third-party programmers, such as BP Microsystems and System General, offer programming hardware that supports serial configuration devices. 4–38 Configuration Handbook, Volume 2 Parameter DCLK DCLK Min Typ Max Unit 0 — — — — 418: SRunner: An Altera Corporation May 2008 ...

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... GND current MAX output current per pin OUT P Power dissipation D Altera Corporation May 2008 Altera Programming Hardware Data Sheet Programming Hardware Manufacturers USB-Blaster Download Cable User Guide ByteBlaster II Download Cable User Guide EthernetBlaster Communications Cable User Guide through 4–30 provide information on absolute maximum ...

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... C – — — Min Max Unit 0.6 × 0 0.6 × 0 0.3 × V – V 0.5 CC – — 0.2 CC — 0.4 V μA – μA – Min Max Unit μA — 50 μA — 100 Altera Corporation May 2008 ...

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... Figure 4–20 package and its pin-out diagram. Figure 4–20. Altera Serial Configuration Device 8-Pin SOIC Package Pin-Out Diagram Figure 4–21 package and its pin-out diagram. Altera Corporation May 2008 Conditions — — Conditions ...

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... After power up, the serial configuration device requires a falling edge on the operation. 16 DCLK 15 ASDI (1) 14 N.C. (1) 13 N.C. (1) N.C. 12 (1) 11 N.C. 10 GND GND, whichever is more CC Description nCS DATA low. The DCLK . . DATA pin is tri-stated. When this nCS signal before beginning any Altera Corporation May 2008 ...

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... Table 4–32. Serial Configuration Device Ordering Codes EPCS1 EPCS4 EPCS16 EPCS64 EPCS128 Note to (1) Altera Corporation May 2008 Pin Type DCLK Input is provided by the FPGA. This signal provides the timing of the serial interface. The data presented on to the serial configuration device on the falling edge of ...

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... ByteBlaster II Download Cable User Guide Configuring Cyclone III Devices chapter in volume 1 of the Cyclone III Device Handbook EthernetBlaster Communications Cable User Guide Operating Requirements for Altera Devices Data Sheet Programming Hardware Manufacturers USB-Blaster Download Cable User Guide Altera Corporation May 2008 ...

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... Updated V Table 4–28. ● Updated I Table 4–29. Updated Figure 4–21 ● information. Altera Corporation May 2008 shows the revision history for this chapter. Changes Made 4–2, 4–5, 4–6, 4–27, and 4–28. Table 4–30. section. section. section. through 4–3 and Tables 4– ...

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... Table 4–31. 4–19. and Table 4–31. Summary of Changes ● Updated chapter to include Stratix II GX, Stratix III, and Cyclone III support for EPCS devices. ● Added information about EPCS16SI8N. — — — — — — — — Altera Corporation May 2008 ...