epm3064a Altera Corporation, epm3064a Datasheet

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... Pin counts ranging from 44 to 256 in a variety of thin quad flat pack (TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier TM (PLCC), and FineLine BGA Hot–socketing support Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance Industrial temperature range EPM3064A EPM3128A 1,250 2,500 64 128 4 8 ...

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... BitBlaster well as programming hardware from third–party manufacturers and any in–circuit tester that supports Jam Programming Language (STAPL) Files (.jam), Jam STAPL Byte-Code Files (.jbc), or Serial Vector Format Files (.svf) Table TM serial download cable as TM Standard Test and 2. Altera Corporation TM ...

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... Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 2. MAX 3000A Speed Grades Device –4 v EPM3032A v EPM3064A EPM3128A EPM3256A EPM3512A Table 3. MAX 3000A Maximum User I/O Pins Device 44–Pin 44–Pin PLCC TQFP ...

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... I/O pin. 4 Logic array blocks (LABs) Macrocells Expander product terms (shareable and parallel) Programmable interconnect array (PIA) I/O control blocks Figure 1 shows the architecture of MAX 3000A devices. MAX+PLUS II and the Sheet. Altera Corporation ...

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... Control I/O Block Note: (1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10 output enables. Logic Array Blocks The MAX 3000A device architecture is based on the linking of high–performance LABs. LABs consist of 16–macrocell arrays, as shown in that is fed by all dedicated input pins, I/O pins, and macrocells. ...

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... Shareable expanders, which are inverted product terms that are fed back into the logic array Parallel expanders, which are product terms borrowed from adjacent macrocells shows a MAX 3000A macrocell. Global Clocks 2 Programmable Register Register Bypass PRN D/T Q Clock/ Enable ENA CLRN Select VCC To PIA Altera Corporation To I/O Control Block ...

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... To set this in the Quartus II software the Assignment Editor and set the Power-Up Level assignment for the register to High. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Global clock signal mode, which achieves the fastest clock–to–output performance. Global clock signal enabled by an active– ...

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... Shareable expanders incur a small delay (t macrocells. Figure 3. MAX 3000A Shareable Expanders 8 ). Figure 3 shows how shareable expanders can feed multiple SEXP Shareable expanders can be shared by any or all macrocells in an LAB. 36 Signals 16 Shared from PIA Expanders Macrocell Product-Term Logic Product-Term Select Matrix Macrocell Product-Term Logic Altera Corporation ...

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... Within each group of eight, the lowest–numbered macrocell can only lend parallel expanders and the highest–numbered macrocell can only borrow them. borrowed from a neighboring macrocell. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet ). For example macrocell PEXP ...

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... PIA signal to drive into the LAB. 10 From Previous Macrocell Product- er Select Matrix Product- Ter Select Matrix To Next Macrocell Figure 5 shows how the PIA signals are routed Preset Macrocell Product- Term Logic Clock Clear Preset Macrocell Product- Term Logic Clock Clear Altera Corporation ...

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... MAX 3000A devices. The I/O control block has global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins subset of the I/O macrocells. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet PIA Signals To LAB ...

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... Figure 6. I/O Control Block of MAX 3000A Devices PIA Note: (1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10 output enables. When the tri–state buffer control is connected to ground, the output is tri-stated (high impedance), and the I/O pin can be used as a dedicated input. When the tri– ...

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... The ISP circuitry in MAX 3000A devices is compliant with the IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Application Note 88 (Using the Jam Language for ISP & ICR via Processor), Application Note 122 (Using Jam STAPL for ISP & ...

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... ISP mode to user mode. The exit ISP stage requires 1 ms. A pulse time to erase, program, or read the EEPROM cells. A shifting time based on the test clock (TCK) frequency and the number of TCK cycles to shift instructions, address, and data into the device. Altera Corporation ...

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... The time required to program a single MAX 3000A device in-system can be calculated from the following formula: t PROG where: t The ISP times for a stand-alone verification of a single MAX 3000A device can be calculated from the following formula: t VER where: t Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Cycle PTCK = t + ------------------------------- - PPULSE f ...

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... Table 5. MAX 3000A In-System Programming Times for Different Test Clock Frequencies Device 10 MHz 5 MHz EPM3032A 2.01 2.01 EPM3064A 2.01 2.02 EPM3128A 2.02 2.04 EPM3256A 2.05 2.09 EPM3512A 2.09 2.18 Table 6. MAX 3000A Stand-Alone Verification Times for Different Test Clock Frequencies Device 10 MHz 5 MHz EPM3032A 0.00 0.01 EPM3064A 0.01 0.01 EPM3128A 0.01 0.02 EPM3256A 0.02 0.03 EPM3512A 0.03 0.06 16 Values TCK Programming t (s) Cycle PPULSE PTCK 2.00 55,000 2.00 105,000 2.00 205,000 2 ...

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... These instructions are used when programming MAX 3000A devices via the JTAG ports with the MasterBlaster, ByteBlasterMV, or BitBlaster cable, or when using a Jam STAPL file, JBC file, or SVF file via an embedded processor or test equipment Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Altera Programming Hardware Data ...

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... EPM3256A EPM3512A Notes: (1) (2) f See Devices) 18 Table 8. MAX 3000A Boundary–Scan Register Length Device EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A Table 9. 32–Bit MAX 3000A Device IDCODE Value Device Version Part Number (16 Bits) (4 Bits) 0001 0111 0000 0011 0010 0001 0111 0000 0110 0100 ...

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... Figure 7. MAX 3000A JTAG Waveforms Captured Table 10 devices. Symbol Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet shows the timing information for the JTAG signals. TMS TDI t JCP t t JCH JCL TCK t JPZX TDO t JSSU Signal ...

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... When MAX 3000A device can drive a 2.5–V device that has 3.3–V CCIO tolerant inputs. ) for the t LPA LAD levels lower than 3.0 V CCIO instead of t OD2 OD1 Output Signal (V) 3.3 5.0 2.5 3 Altera Corporation , LAC IC . Inputs can 5.0 v ...

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... EEPROM bit and all internal logic elements ensures 100% programming yield. AC test measurements are taken under conditions equivalent to those shown in erased during early stages of the production flow. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet current specification should be OL Figure 8 ...

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... Device Output 620 Ω [481 Ω] C1 (includes jig capacitance) Device input rise and fall times < Note (1) Min Max –0.5 4.6 –2.0 5.75 –25 25 –65 150 –65 135 135 Altera Corporation VCC To Test System Unit ° C ° C ° C ...

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... I I Tri–state output off–state current OZ R Value of I/O pin pull–up resistor when programming in–system or during power–up Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Conditions (10) (3) Commercial range Industrial range Commercial range Industrial range (11) ...

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... C. For in-system programming support between –40° shows the typical output drive characteristics of MAX 3000A Min Max Unit and V are CCINT CCIO Table 13 on page 23. parameter refers OH parameter refers to OL voltage level for POR is CCINT Altera Corporation ...

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... Signals can be driven into MAX 3000A devices before and during power-up without damaging the device. In addition, MAX 3000A devices do not drive out during power-up. Once operating conditions are reached, MAX 3000A devices operate as specified by the user. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet 3.3 V 150 ...

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... Control Delay t LAC Shared Expander Delay t SEXP Figure 11 Figure 10. MAX 3000A Output Register Delay Delay OD1 OD2 t t PRE OD3 t t CLR COMB I/O Delay shows the timing relationship Altera Corporation ...

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... All timing characteristics are measured at 1.5 V. Shared Expander Parallel Expander Data or Enable (Logic Array Output) Input or I/O Pin Register to PIA Register Output Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Combinatorial Mode t IN Input Pin t IO I/O Pin PIA Delay ...

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... Minimum global clock CNT period f Maximum internal CNT global clock frequency t Minimum array clock ACNT period f Maximum internal ACNT array clock frequency 28 through 23 show EPM3032A, EPM3064A, EPM3128A, Note (1) Conditions –4 Min Max 4.5 ( 4.5 (2) (2) 2.9 (2) 0 1.0 3.0 2.0 2 ...

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... Combinatorial delay COMB t Array clock delay IC t Register enable time EN t Global control delay GLOB t Register preset time PRE t Register clear time CLR Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Note (1) Conditions –4 Min Max 0.7 0.7 1.9 0.5 1.5 0 ...

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... MAX 3000A Programmable Logic Device Family Data Sheet Table 17. EPM3032A Internal Timing Parameters (Part Symbol Parameter t PIA delay PIA t Low–power adder LPA Table 18. EPM3064A External Timing Parameters Symbol Parameter t Input to non–registered PD1 output t I/O input to non–registered PD2 output ...

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... Table 19. EPM3064A Internal Timing Parameters (Part Symbol Parameter t Input pad and buffer delay IN t I/O input pad and buffer IO delay t Shared expander delay SEXP t Parallel expander delay PEXP t Logic array delay LAD t Logic control array delay LAC t Internal output enable delay ...

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... MAX 3000A Programmable Logic Device Family Data Sheet Table 19. EPM3064A Internal Timing Parameters (Part Symbol Parameter t Register clear time CLR t PIA delay PIA t Low–power adder LPA Table 20. EPM3128A External Timing Parameters Symbol Parameter t Input to non– PD1 registered output t I/O input to non– ...

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... V = 2.5 V CCIO t Output buffer enable delay, ZX3 slow slew rate = 2 3.3 V CCIO t Output buffer disable delay Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Note (1) Conditions –5 Min Max (2), (4) 192.3 Conditions –5 Min Max ...

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... Conditions –7 Min ( (2) (2) 5.2 (2) 0 1.0 3.0 3.0 (2) 2.7 (2) 0.3 (2) 1.0 3.0 3.0 (3) 3.0 Speed Grade –7 –10 Min Max Min Max 2.1 2.9 1.0 1.3 1.2 1.6 0.9 1.3 1.7 2.2 1.0 1.3 1.6 2.0 2.0 2.7 2.0 2.7 2.0 2.6 4.0 5.0 Speed Grade –10 Max Min Max 7.5 10 7.5 10 6.9 0.0 4.8 1.0 6.4 4.0 4.0 3.6 0.5 7.3 1.0 9.7 4.0 4.0 4.0 Altera Corporation Unit Unit ...

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... 3.3 V CCIO t Output buffer enable delay, slow ZX1 slew rate = off V CCIO t Output buffer enable delay, slow ZX2 slew rate = off V CCIO Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Note (1) Conditions Min (2) (2), (4) 126.6 (2) (2), (4) 126.6 Conditions ...

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... Min 2.1 0.9 (2) (5) Note (1) Conditions Speed Grade -7 Min Max (2) 7 (2) 7.5 (2) 5.6 (2) 0.0 3.0 0 1.0 4.7 3.0 3.0 (2) 2.5 Speed Grade Unit –10 Max Min Max 9.0 10.0 ns 4.0 5.0 ns 2.9 ns 1.2 ns 1.2 1.6 ns 0.8 1.2 ns 1.6 2.1 ns 1.0 1.3 ns 1.5 2.0 ns 2.3 3.0 ns 2.3 3.0 ns 2.4 3.2 ns 4.0 5.0 ns Unit -10 Min Max 10.0 ns 10.0 ns 7.6 ns 0.0 ns 3.0 ns 0.0 ns 1.0 6.3 ns 4.0 ns 4.0 ns 3.5 ns Altera Corporation ...

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... Output buffer and pad delay, OD1 slow slew rate = off V = 3.3 V CCIO t Output buffer and pad delay, OD2 slow slew rate = off V = 2.5 V CCIO Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Note (1) Conditions Speed Grade -7 Min Max (2) 0 (2) 1.0 7 ...

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... 9 4.0 2.1 0.6 1.6 1.4 1.3 0.6 1.8 1.0 1.7 1.0 1.0 (2) 3.0 (5) 4 and t LAD LAC IC EN SEXP ACL Unit -10 Min Max 6.5 ns 5.0 ns 5.5 ns 10.0 ns 5.0 ns 3.0 ns 0.8 ns 1.6 ns 1.4 ns 1.7 ns 0.8 ns 2.3 ns 1.3 ns 2.2 ns 1.4 ns 1.4 ns 4.0 ns 5.0 ns Table 13 on page 23. See parameter LPA parameter into the signal LAD parameters for macrocells CPPW Altera Corporation ...

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... RPT File = Highest clock frequency to the device = Average percentage of logic cells toggling at each clock LC (typically 12.5%) = Constants (shown in Equation Constants CC Device EPM3032A EPM3064A EPM3128A EPM3256A EPM3512A calculation provides an I CCINT and 13 show the typical supply current versus frequency for , in MHz) for MAX 3000A ...

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... V CC 140 Room Temperature 120 100 Typical I CC Active (mA Low Power 100 Frequency (MHz) 40 EPM3064A 227.3 MHz High Speed Typical I CC Active (mA) 144.9 MHz 200 250 192.3 MHz High Speed 108.7 MHz 200 250 3 ...

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... V CC Room Temperature 250 200 Typical I CC 150 Active (mA) 100 Low Power Frequency (MHz) Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet EPM3512A 172.4 MHz High Speed Typical I Active (mA) 102.0 MHz 100 200 600 Room Temperature ...

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... PLCC 42 through 18 show the package pin–out diagrams for Pin 1 39 I/O I/O/TDI 38 I/O/TDO I/O 37 I/O I/O 36 GND GND 35 VCC I/O 34 I/O I/O 33 I/O I/O/TMS 32 I/O/TCK 31 I/O I/O VCC 30 GND 29 I/O I/O GND Pin 12 Pin 34 I/O I/O/TDO I/O GND VCC EPM3032A I/O EPM3064A I/O I/O/TCK I/O GND I/O Pin 23 44-Pin TQFP Altera Corporation ...

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... Figure 15. 100–Pin TQFP Package Pin–Out Diagram Package outline not drawn to scale. Figure 16. 144–Pin TQFP Package Pin–Out Diagram Package outline not drawn to scale Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Pin 1 EPM3064A EPM3128A Pin 26 . Indicates location of Pin 1 Pin 1 ...

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... MAX 3000A Programmable Logic Device Family Data Sheet Figure 17. 208–Pin PQFP Package Pin–Out Diagram Package outline not drawn to scale Pin 1 Pin EPM3256A EPM3512A Pin 157 Pin 105 Altera Corporation ...

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... The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.5: ■ Version 3.4 The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.4: ■ Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet . ...

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