FAN7392 Fairchild Semiconductor, FAN7392 Datasheet

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FAN7392

Manufacturer Part Number
FAN7392
Description
The FAN7392 is a monolithic high- and low-side gate drive IC, that can drive high-speed MOSFETs and IGBTs that operate up to +600V
Manufacturer
Fairchild Semiconductor
Datasheet

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FAN7392 Rev. 1.0.3
© 2009 Fairchild Semiconductor Corporation
FAN7392
High-Current, High- and Low-Side, Gate-Drive IC
Features
Applications
Ordering Information
Floating Channel for Bootstrap Operation to +600V
3A/3A Sourcing/Sinking Current Driving Capability
Common-Mode dv/dt Noise Canceling Circuit
3.3V Logic Compatible
Separate Logic Supply (V
Under-Voltage Lockout for V
Cycle-by-Cycle Edge-Triggered Shutdown Logic
Matched Propagation Delay for Both Channels
Outputs In-phase with Input Signals
Available in 14-DIP and 16-SOP (Wide) Packages
High-Speed Power MOSFET and IGBT Gate Driver
Server Power Supply
Uninterrupted Power Supply (UPS)
Telecom System Power Supply
Distributed Power Supply
Motor Drive Inverter
Part Number
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
FAN7392MX
FAN7392M
FAN7392N
Temperature Range
DD
-40°C to +125°C
) Range from 3.3V to 20V
CC
Operating
and V
BS
Package
14-PDIP
16-SOP
Description
The FAN7392 is a monolithic high- and low-side gate
drive IC, that can drive high-speed MOSFETs and IGBTs
that operate up to +600V. It has a buffered output stage
with all NMOS transistors designed for high pulse current
driving capability and minimum cross-conduction. Fair-
child’s high-voltage process and common-mode noise
canceling techniques provide stable operation of the
high-side driver under high dv/dt noise circumstances.
An advanced level-shift circuit offers high-side gate driver
operation up to V
inputs are compatible with standard CMOS or LSTTL
output, down to 3.3V logic. The UVLO circuit prevents
malfunction when V
fied threshold voltage. The high-current and low-output
voltage drop feature makes this device suitable for half-
and full-bridge inverters, like switching-mode power sup-
ply and high-power DC-DC converter applications.
14-PDIP
Eco Status
RoHS
S
CC
=-9.8V (typical) for V
and V
BS
are lower than the speci-
16-SOP
Packing Method
Tape and Reel
BS
Tube
Tube
February 2010
www.fairchildsemi.com
=15V. Logic

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FAN7392 Summary of contents

Page 1

... Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 Description The FAN7392 is a monolithic high- and low-side gate drive IC, that can drive high-speed MOSFETs and IGBTs that operate up to +600V. It has a buffered output stage with all NMOS transistors designed for high pulse current driving capability and minimum cross-conduction. Fair- child’ ...

Page 2

... Typical Application Diagrams 15V HIN Controller SD LIN Figure 1. Typical Application Circuit (Referenced 14-DIP) 15V HIN Controller SD LIN Figure 2. Typical Application Circuit (Referenced 16-SOP) © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0 BOOT HIN BOOT ...

Page 3

... TRIGGER INPUT LIN 14 CYCLE-By-CYCLE SD 13 EDGE TRIGGERED SHUTDOWN Pin 4, 5, 9,10 and 16 are no connection Figure 4. Functional Block Diagram (Referenced 16-SOP) © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 NOISE CANCELLER HS(ON/OFF) UVLO VSS/COM LS(ON/OFF) LEVEL SHIFT NOISE CANCELLER HS(ON/OFF) UVLO VSS/COM ...

Page 4

... Pin Definitions 14-Pin 16-Pin 4,8, 10, 16 © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0 COM LIN HIN ...

Page 5

... Low-Side Output Voltage LO V Logic Supply Voltage DD V Logic Supply Offset Voltage SS V Logic Input Voltage IN T Operating Ambient Temperature A © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 =25°C unless otherwise specified. A Characteristics 14-PDIP ( 16-SOP 14-PDIP 16-SOP ) under any circumstances. D Parameter 5 Min. Max. ...

Page 6

... SS Allowable Negative Signal Propagation to HO © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 =COM=0V and T =25°C, unless otherwise specified. The and are applicable to the respective input leads: HIN, LIN, and SD. The V and COM and are applicable to the respective output leads: HO and LO. ...

Page 7

... Shutdown propagation Delay Time sd t Turn-On Rise Time r t Turn-Off Fall Time f MT Delay Matching, HO & LO Turn-On/Off Note: 4. These parameters guaranteed by design. © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 =COM=0V, C =1000pF, T =25°C, unless otherwise specified. LOAD A Conditions V = =0V S ...

Page 8

... Temperature [°C] Figure 8. Turn-On Rise Time vs. Temperature -40 - Temperature [°C] Figure 10. Turn-On Delay Matching vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 200 180 160 140 120 100 60 80 100 120 -40 -20 Figure 7. Turn-Off Propagation Delay ...

Page 9

... Figure 14. Quiescent V CC vs. Temperature 1000 800 600 400 200 0 -40 - Temperature [°C] Figure 16. Operating V CC vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 (Continued 100 120 -40 Figure 13. Logic Input High Bias Current 120 100 ...

Page 10

... UVLO+ vs. Temperature CC 9.5 9.0 8.5 8.0 -40 - Temperature [°C] Figure 20. V UVLO+ vs. Temperature BS 1.5 1.0 0.5 0.0 -40 - Temperature [°C] Figure 22. High-Level Output Voltage vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 (Continued) 9.5 9.0 8.5 8.0 7.5 - 100 120 Figure 19. V 9.5 9.0 8.5 8.0 7.5 - 100 120 Figure 21 ...

Page 11

... Figure 26. Allowable Negative V vs. Temperature - -10 -12 -14 - Supply Voltage [V] Figure 28. Allowable Negative Vs Voltage for HIN Signal Propagation to High Side vs. Supply Voltage © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 (Continued 15V 100 120 -40 12 ...

Page 12

... Switching Time Definitions HIN SD LIN Figure 29. Switching Time Test Circuit (Referenced 14-DIP) HIN LIN HIN LIN HO LO © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 15V 1nF HIN 15V V LIN 10μF ...

Page 13

... Switching Time Definitions HIN LIN © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 (Continued) 50 90% Figure 32. Shutdown Waveform Definition 50 10% 10% MT Figure 33. Delay Matching Waveform Definitions 13 50% MT 90% 90 www.fairchildsemi.com ...

Page 14

... Figure 35. V Waveforms During Q1 Turn-Off S © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 Figure 36 and Figure 37 show the commutation of the load current between high-side switch, Q1, and low-side freewheelling diode, D3, in same inverter leg. The para- sitic inductances in the inverter circuit from the die wire ...

Page 15

... Pulse Width [ns] Figure 38. Negative V Transient Chracteristic S Even though the FAN7392 has been shown able to han- dle these negative V tranient conditions strongly S recommended that the circuit designer limit the negative V transient as much as possible by careful PCB layout S to minimized the value of parasitic elements and compo- nent use ...

Page 16

... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 8 6.60 6. ...

Page 17

... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 10.30±0.20 A 8.890 ...

Page 18

... Fairchild Semiconductor Corporation FAN7392 Rev. 1.0.3 18 www.fairchildsemi.com ...

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