FM25CL64-DG Cypress Semiconductor, FM25CL64-DG Datasheet
FM25CL64-DG
Specifications of FM25CL64-DG
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FM25CL64-DG Summary of contents
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... Pin Name /CS /WP /HOLD SCK SI SO VDD VSS Ordering Information FM25CL64-G † FM25CL64-GTR † FM25CL64-DG drop-in FM25CL64-DGTR FM25CL64-S * Device FM25CL64-STR * † Grade 3 AEC-Q100 Qualified * End of life. Last time buy June 2009. 1850 Ramtron Drive, Colorado Springs, CO 80921 VDD 1 8 HOLD 2 7 SCK ...
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... SO may be connected to SI for a single pin data interface. VDD Supply Power Supply (2.7V to 3.65V) VSS Supply Ground Rev. 3.5 Feb. 2011 13 Counter Data I/O Register Nonvolatile Status Figure 1. Block Diagram FM25CL64 2,048 x 32 FRAM Array Register Page ...
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... This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25CL64 due to its fast write cycle and high endurance as compared with EEPROM. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly ...
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... SPI Mode 0: CPOL=0, CPHA=0 7 SPI Mode 3: CPOL=1, CPHA=1 7 Rev. 3.5 Feb. 2011 SO SI SCK SO FM25CL64 FM25CL64 CS HOLD Figure 4. SPI Modes 0 & 3 FM25CL64 SI SCK HOLD MOSI : Master Out Slave In MISO : Master In Slave Out SS : Slave Select Page ...
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... SCK. Command Structure There are six commands called op-codes that can be issued by the bus master to the FM25CL64. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent operations ...
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... Status Register. Reading Status provides information about the current state of the write protection features. Following the RDSR op- code, the FM25CL64 will return one byte with the contents of the Status Register. The Status Register is described in detail in a later section. ...
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... The SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the F-RAM technology. Unlike SPI-bus EEPROMs, the FM25CL64 can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed. Write Operation All writes to the memory begin with a WREN op- code with /CS being asserted and deasserted ...
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... Address MSB 13-bit Address MSB Figure 10. Memory Read FM25CL64 Data LSB MSB LSB ...
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... DD Min Typ 2 -0.3 V – other inputs -0.3V FM25CL64 Ratings -1.0V to +5.0V -1.0V to +5.0V and V < V +1. -55° 125°C 300° C 4kV 300V MSL-1 Max Units Notes 3. 0. µA 2 ±1 µA 3 ±1 µA ...
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... L V 2.7 to 3.0V DD Min Max 3.3V) DD Min - - 10% and 90 0 FM25CL64 V 3.0 to 3.65V DD Min Max Units Notes 0 20 MHz 2 2,3 ...
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... Serial Data Bus Timing tCSU 1/fCK tH tSU /Hold Timing Data Retention (V = 2.7V to 3.65V, +85°C) DD Parameter Data Retention Rev. 3.5 Feb. 2011 tF tR tODV tOH Min Max Units 45 - Years FM25CL64 tD tCSH tCL tCH tOD Notes Page ...
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... Legend: XXXXX= part number, P= package type, T= temperature (A=automotive, blank=ind.) LLLLLLL= lot code XXXXXX-PT RIC=Ramtron Int’l Corp, YY=year, WW=work week LLLLLLL RICYYWW Example: FM25CL64, “Green” SOIC package, Year 2006, Work Week 29 FM25CL64G A60013G1 RIC0629 Rev. 3.5 Feb. 2011 Recommended PCB Footprint 3 ...
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... Legend: R=Ramtron, G=”green”/RoHS TDFN package, XXXX=base part number LLLL= lot code, RGXXXX YY=year, WW=work week LLLL YYWW Example: “Green” TDFN package, FM25CL64, Lot 0013, Year 2006, Work Week 29 RG5L64 0013 0629 Rev. 3.5 Feb. 2011 Exposed metal pad. Do not connect to anything except Vss ...
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... Added tape and reel ordering information. Added note that SOIC device is Grade 3 AEC-Q100 qualified. Added last time buy notice on –S ordering numbers. 3.5 2/18/2011 Not recommended for new designs. Alternative: FM25CL64B. Rev. 3.5 Feb. 2011 spec limits. Removed 5MHz I DD FM25CL64 entry. ...