FM93C86 Fairchild Semiconductor, FM93C86 Datasheet
FM93C86
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FM93C86 Summary of contents
Page 1
... Disable operations. This device is fabricated using Fairchild Semiconductor floating-gate CMOS process for high reliability, high endurance and low power consumption. “LZ” and “L” versions of FM93C86A offer very low standby current making them suitable for low power applications. This device is offered in both SO and DIP packages. ...
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... Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the FM93C86A Rev. C ...
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... CSH t DI Hold Time DIH t Output Delay Status Valid Hi Write Cycle Time WP FM93C86A Rev. C.1 (Note 1) -65°C to +150°C Ambient Operating Temperature FM93C86A +6.5V to -0.3V FM93C86AE FM93C86AV +300°C Power Supply ( 2000V V = 4.5V to 5.5V unless otherwise specified SK=1 ...
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... KHz (Note 6) C Output Capacitance OUT C Input Capacitance IN 2.7V ≤ V ≤ 5.5V 0.3V/1.8V CC (Extended Voltage Levels) 4.5V ≤ V ≤ 5.5V 0.4V/2.4V CC (TTL Levels) FM93C86A Rev. C.1 (Note 1) -65°C to +150°C Ambient Operating Temperature FM93C86AL/LZ +6.5V to -0.3V FM93C86ALE/LZE FM93C86ALV/LZV +300°C Power Supply ( 2000V V = 2.7V to 4.5V unless otherwise specified. Refer ...
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... This is an active high input pin to FM93C86A EEPROM (the device) and is generated by a master that is controlling the device. A high level on this pin selects the device and a low level deselects the device. All serial communications with the device is enabled only when this pin is held high. However this pin cannot be permanently tied high rising edge on this signal is required to reset the internal state-machine to accept a new cycle ...
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... Opcode and Address) for this WEN instruction should be issued as listed under Table 1 or Table 2. The device becomes write- enabled at the end of this cycle when the CS signal is brought low. Execution of a READ instruction is independent of WEN instruc- tion. Refer Write Enable cycle diagram. FM93C86A Rev. C.1 Opcode Field Address Field 10 A10 A9 ...
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... The Erase all instruction will program all locations to logical “1” state. Input information (Start bit, Opcode and Address) for this WDS instruction should be issued as listed under Table 1 or Table FM93C86A Rev. C.1 2. The self-timed programming cycle starts with the clocking of the last data bit (DO). It takes t Electrical Characteristics table) for the internal programming cycle to finish ...
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... > > n’ =A10 > > n’ FM93C86A Rev. C SKH SKL t DIH ...
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... -> -x-x-x-x-x-x-x- > D on't Care, can =A10; D 93C86 > 0 -1-x-x-x-x-x-x-x-x-x; (x -> Don't C are, can FM93C86A Rev. C ...
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... FM93C86A Rev. C ...
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... All lead tips Typ. All Leads FM93C86A Rev. C.1 0.189 - 0.197 (4.800 - 5.004 0.228 - 0.244 (5.791 - 6.198 Lead #1 IDENT 0.053 - 0.069 (1.346 - 1.753) 8¡ ...
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... English Français Italiano Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. FM93C86A Rev. C.1 0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) ...